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PCI bus 0 is connected to the Tsi148 device and PMCspan bridge. PCI bus 0 is configured for 133
MHz PCI-X mode.
The MV64360 PCI interfaces are fully PCI rev. 2.2 and PCI-X rev 1.0 compliant and support both
address and data parity checking. The MV64360 contains all of the required PCI configuration
registers. All internal registers, including the PCI configuration registers, are accessible from
the CPU bus or the PCI buses.
4.6.5
Gigabit Ethernet MACs
The MVME6100 supports two 10/100/1000Mb/s full duplex Ethernet ports connected to the
front panel via the MV64360 system controller. Ethernet access is provided by front panel RJ-
45 connectors with integrated magnetics and LEDs. Port 1 is a dedicated Gigabit Ethernet port
while a configuration header is provided for port 2 front or rear P2 access Refer to
Ethernet and Transition Module Options Header (J30)
Each Ethernet interface is assigned an Ethernet Station Address. The address is unique for each
device. The Ethernet Station Addresses are displayed on labels attached to the PMC front-panel
keep-out area.
The MV64360 is not integrated with a PHY for the Ethernet interfaces. External PHY is the
Broadcom BCM5461S 10/100/1000BaseT Gigabit transceiver with SERDES interface. Refer to
Appendix C, Related Documentation
4.6.6
SRAM
The MV64360 integrates 2Mb of general-purpose SRAM. It is accessible from the CPU or any of
the other interfaces. It can be used as fast CPU access memory (6 cycles latency) and for off
loading DRAM traffic. A typical usage of the SRAM can be a descriptor RAM for the Gigabit
Ethernet ports.
4.6.7
General-Purpose Timers/Counters
There are four 32-bit wide timers/counters on the MV64360. Each timer/counter can be
selected to operate as a timer or as a counter. The timing reference is based on the MV64360
Tclk input, which is set at 133 MHz. Each timer/counter is capable of generating an interrupt.
Refer to the MV64360 Data Sheet, listed in
information and programming details.
MVME6100 Single Board Computer Installation and Use (6806800D58E)
for more information.
for more information.
Appendix C, Related
Functional Description
Front/Rear
Documentation, for additional
65
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