TYAN S8005 User Manual page 67

3.7.1.1 Memory Configuration
Bank Interleaving
Enable or Disable Bank Memory Interleaving.
Auto / Disabled
Channel Interleaving
Enable or Disable Channel Memory Interleaving.
Disabled / Address bits 6 / Address bits 12 / XOR of Address bits [20:16,
6] / XOR of Address bits [20:16, 9]
Enable Clock to All DIMMs
Enable unused clocks to DIMMs even memory slots are not populated.
Disabled / Enabled
MemClk Tristate C3/ATLVID
Enable or Disable MemClk Tri-Stating during C3 and Alt VID.
Disabled / Enabled
Memory Hole Remapping
Enable or Disable Memory Hold remapping.
Enabled / Disabled
DCT Unganged Mode
This allows selection of unganged DRAM mode (64-bit width).
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