Chipset; Overview; Intel Dual I/O Hub (Ioh); Intel Quickpath Architecture (Qpi) - Dell PowerEdge T710 Technical Manual

Dell

8 Chipset

8.1 Overview

The Dell™ PowerEdge™ T710 planar incorporates the Intel
I/O and processor interfacing. This chipset is designed to support the Intel Xeon 5500 and 5600
processor series family, QuickPath Interconnect, DDR3 memory technology, and PCI Express
Generation 2. The chipset consists of the Intel 5520 chipset I/O Hub (IOH) and ICH9.

8.2 Intel Dual I/O Hub (IOH)

The T710 motherboard incorporates the Intel 5520 chipset IOH to provide a link between the Intel
Xeon processor(s) 5500 and 5600 series and I/O components. The main components of the IOH consist
of two full-width QPI links (one to each processor), 72 lanes of PCIe Gen2, and a x4 ESI link to
connect directly to the South Bridge.
The IOH supports a special mode to work with DP processors that allows two IOHs to appear as a
single IOH to the processors in the system. This mode results in special behavior in the link and
protocol layers. Each IOH will have a unique NodeID for communication between each other, but only
the legacy IOH's NodeID will be exposed to the processor.

8.3 Intel Quickpath Architecture (QPI)

The QuickPath Architecture consists of serial point-to-point interconnects for the processors and the
IOH. The T710 has a total of four QuickPath Interconnect (QPI) links including one link connecting the
processors and links connecting both processors with the IOH and links connecting both IOHs. Each
link consists of 20 lanes (full-width) in each direction with a link speed of 6.4 GT/s. An additional
lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.
The QuickPath Architecture implemented in the IOH and processors features four layers:

Physical layer—Consists of the actual connection between components. Supports Polarity
Inversion and Lane Reversal for optimizing component placement and routing.

Link layer—Responsible for flow control and the reliable transmission of data.

Routing layer—Responsible for the routing of QPI data packets.

Protocol layer—Responsible for high-level protocol communications, including the
implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence
protocol.

8.4 PCI Express Generation 2

PCI Express is a serial point-to-point interconnects for I/O devices. PCIe Gen2 doubles the signaling
bit rate of each lane from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible
with Gen1 transfer rates.

8.5 Intel Direct Media Interface (DMI)

The DMI previously called the Enterprise Southbridge Interface) connects the IOH with the Intel I/O
Controller Hub (ICH). The DMI is equivalent to a x4 PCIe Gen1 link with a transfer rate of 1 GB/s in
each direction.

8.6 Intel I/O Controller Hub 9 (ICH9)

ICH9 is a highly integrated I/O controller, supporting the following functions:
PowerEdge T710 Technical Guide
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Xeon 5520 processor series chipset for
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