AOpen AX4B MAX Manual page 97
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Also See for AX4B MAX:
- Easy installation manual (9 pages) ,
- Online manual (110 pages) ,
- Easy installation manual (8 pages)
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Channel for communications between the memory and surrounding devices.
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The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
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The EDO DRAM technology is actually very similar to FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory
output data to start the pre-charge activity, EDO DRAM holds the memory data valid until the next memory access cycle, that is
similar to pipeline effect and reduces one clock state.
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Also known as E
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technology is different. Size of EEPROM is much smaller than flash ROM.
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Flash ROM
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can be re-programmed by electronic signals, but the interface
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