5.6.3.2 Ultra Dma Data Burst Timing Requirements - Fujitsu MPG3409AT Product Manual

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.19 Ultra DMA data burst timing requirements (1 of 2)
MODE 0 MODE 1
(in ns) (in ns)
NAME
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t 240 160
2CYCTYP
t 112 73
CYC
t 230 153
2CYC
t 15 10
DS
t 5 5
DH
t 70 48
DVS
t 6.2 6.2
DVH
t 15 10
CS
t 5 5
CH
t 70 48
CVS
t 6.2 6.2
CVH
t 0 0
ZFS
t 70 48
DZFS
t 230
FS
t 0 150 0
LI
t 20 20
MLI
T 0 0
UI
5 - 98
MODE 2 MODE 3
(in ns) (in ns)
120 90
54 39
115 86
7 7
5 5
31 20
6.2 6.2
7 7
5 5
31 20
6.2 6.2
0 0
31 20
200 170 130
150 0 150 0 100
20 20
0 0
C141-E110-03EN
MODE 4 MODE 5
(in ns) (in ns)
60 40 Typical sustained average two
cycle time
25 16.8 Cycle time allowing for
asymmetry and clock variations
(from STROBE edge to STROBE
edge)
57 38 Two cycle time allowing for clock
variations (from rising edge to
next rising edge or from falling
edge to next falling edge of
STROBE)
5 4 Data setup time at recipient (from
data valid until STROBE edge)
(*2), (*5)
5 4.6 Data hold time at recipient (from
STROBE edge until data may
become invalid) (*2), (*5)
6.7 4.8 Data valid setup time at sender (from
data valid until STROBE edge) (*3)
6.2 4.8 Data valid hold time at sender
(from STROBE edge until data
may become invalid) (*3)
5 5 CRC word setup time at device
(*2)
5 5 CRC word hold time device (*2)
6.7 10 CRC word valid setup time at host
(from CRC valid until DMACK-
negation) (*3)
6.2 10 CRC word valid hold time at
sender (from DMACK-negation
until CRC may become invalid)
(*3)
0 35 Time from STROBE output
released-to-driving until the first
transition of critical timing
6.7 25 Time from data output released-
to-driving until the first transition
of critical timing
120 90 First STROBE time (for device to
first negate DSTROBE from
STOP during a data in burst)
0 100 0 75 Limited interlock time (*1)
20 20 Interlock time with minimum (*1)
0 0 Unlimited interlock time (*1)
COMMENT