Physical Interface; Interface Signals - Fujitsu MPG3409AT Product Manual

5.1

Physical Interface

5.1.1

Interface signals

Table 5.1 shows the interface signals.
Cable select
Chip select 0
Chip select 1
Data bus bit 0
Data bus bit 1
Data bus bit 2
Data bus bit 3
Data bus bit 4
Data bus bit 5
Data bus bit 6
Data bus bit 7
Data bus bit 8
Data bus bit 9
Data bus bit 10
Data bus bit 11
Data bus bit 12
Data bus bit 13
Data bus bit 14
Data bus bit 15
Device active or slave present
Device address bit 0
Device address bit 1
Device address bit 2
DMA acknowledge
DMA request
Interrupt request
I/O read
DMA ready during Ultra DMA data in bursts
Data strobe during Ultra DMA data out bursts
I/O ready
DMA ready during Ultra DMA data out bursts
Data strobe during Ultra DMA data in bursts
I/O write
Stop during Ultra DMA data bursts
Passed diagnostics
Cable type detection
Reset
Note See signal descriptions
5 - 2
Table 5.1

Interface signals

Description
C141-E110-03EN
Host Dir Dev Acrorym
see note CSEL
CS0–
CS1–
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
see note DASP–
DA0
DA1
DA2
DMACK–
DMARQ
INTRQ
DIOR–
HDMARDY–
HSTROBE
IORDY
DDMARDY–
DSTROBE
DIOW–
STOP
see note PDIAG–
CBLID–
RESET–