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Signal name
Pin
INTRQ
IOCS16-
DA0-2
33,35,36
PDIAG-:CBLID-
(*1)
CS0-
CS1-
*1: PDIAG-:CBLID- (Passed diagnostics: Cable assembly type identifier
K6610007
Rev.5
02.14.'03
Table 6.2 Signal List(2/3)
I/O type
31
O
This is an interrupt signal for the host system. This signal is
asserted by a selected device when the nIEN bit in the Device
Control Register is "0". In other cases, this signal should be a high
impedance state.
32
O
This signal indicates to the host that the 16-bit data port has been
addressed and a 16-bit word can be read or written to the device.
I
This is a register address signal from the host system.
34
I/O
The PDIAG- signal is asserted by Device 1 to indicate to Device 0
that it has completed diagnostics. This signal is pulled up inside the
device.
The host may sample CBLID- after a power-on or hardware reset in
order to detect the presence or absence of an 80-conductor cable
assembly by performing the following steps:
a) The host shall wait until the power on or hardware reset
b) If Device 1 is present, the host should issue IDENTIFY DEVICE
If the host detects that CBLID- is connected to ground, an 80-
conductor cable assembly is installed in the system. If the host
detects that this signal is not connected to ground, an 80-conductor
cable assembly is not installed in the system.
37
I
This device chip selection signal is used to select the Command
Block Registers from the host system.
38
I
This device chip selection signal is used to select the Control Block
Registers from the host system.
sequence is complete for all devices on the cable;
or IDENTIFY PACKET DEVICE and use the returned data to
determine that Device 1 is compliant with ATA-3 or subsequent
standards. Any device compliant with ATA-3 or subsequent
standards releases PDIAG- no later than after the first
command following a power on or hardware reset sequence.
- 29 -
Description
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