Ultra Dma Data Transfer Timing - Hitachi DK23FB-60 - Travelstar 60 GB Specifications

6.4.2 Ultra DMA Data Transfer Timing

Figures 6-8 through 6-12 and 6-13 through 17 define the timings associated with all phases of Ultra DMA data
transfer.
D M AR Q
(device)
D M AC K-
(host)
ST O P
(host)
H D M AR D Y-
(host)
D ST RO BE
(device)
D D (15:0)
D A0, D A1, D A2,
C S0-, C S1-
Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are not in effect until DMARQ
and DMACK are asserted.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode3(ns) Mode4(ns) Mode5(ns
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t 70
DVS
t 6.2
DVH
t 230
FS
t 0
UI
t 10
AZ
t 0
ZAD
t 20 70
ENV
t 0
ZIORDY
t 0
ZFS
t 70
DZFS
t 20
ACK
K6610007
Rev.5
02.14.'03
Figure 6-8 Initiating an Ultra DMA Read
t
UI
t t
ACK
t
t
ACK
ENV
t
ZIO RD Y
t
AZ
t
ACK
48 31
6.2 6.2
200 170
0 0
10 10
0 0
20 70 20 70
0 0
0 0
48 31
20 20
t
FS
ENV
t
ZAD
t
FS
t
ZAD
t
ZFS
t
DZFS
t
DVS
20 6.7
6.2 6.2
130 120
0 0
10 10
0 0
20 55 20 55
0 0
0 0
20 6.7
20 20
- 100 -
t
DVH
Description
)
4.8 Data valid setup time at sender
4.8 Data valid hold time at sender
90 First strobe
0 Unlimited interlock
10 Maximum time allowed for output
drivers to release
0 Maximum delay time for output
drivers turning on
20 50 Envelope time
0
Minimum time waiting before
driving IORDY
35
Time from STROBE output
released-to-driving until the first
transition of critical timing
25 Time from data output released-
to-driving until the first transition
of critical timing
20 Setup and hold times before
assertion and negation of
DMACK_