9.2 Alternate Status Register
Table 60: Alternate Status Register
7
6
BSY
RDY
This register contains the same information as the Status Register. The only difference between this register and the
Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a
pending interrupt.
9.3 Command Register
This register contains the command code being sent to the device. Command execution begins immediately after
this register is written. The command set is shown in Table 74: 'Command Set (1 of 2)" on page 109 and Table
75: 'Command Set (2 of 2)" on page 110. All other registers required for the command must be set up before writ-
ing to the Command Register.
9.4 Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access. At the end of the com-
mand, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16–23. At the end of the command, this register is updated to reflect the
current LBA Bits 16–23.
The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 16-23 and the
"previous content" contains Bits 40-47.
9.5 Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the
command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 8–15. At the end of the command, this register is updated to reflect the
current LBA Bits 8–15.
The cylinder number may be from zero to the number of cylinders minus one (1).
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15 and the
"previous content" contains Bits 32-39.
5
4
3
DSC/
DF
DRQ
SERV
Deskstar 7K400 Hard Disk Drive Specification
2
1
0
COR
IDX
ERR
68