Write Dma Queued (Cch); Table 171. Write Dma Queued Command Cah/Cbh) - Hitachi 7K400 - Deskstar Hard Drive Specifications

12.52 Write DMA Queued (CCh)

Table 172: Write DMA Queued Command CAh/CBh)
Command Block Output Registers
Register
Data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
7 6 5
CRC UNC 0
V 0 0
This command executes in a similar manner to a WRITE DMA command. The device may perform a bus release
or it may execute the data transfer without performing a bus release if the data is ready to be transferred.
If the device performs a bus release, the host shall reselect the device using the SERVICE command.
When the data transfer has begun, the device does not perform a bus release until the entire data transfer has been
completed.
Output parameters to the device
Feature
Sector Count
Sector Number
Cylinder High/Low
H
Input parameters from the device on bus release
Sector Count
Sector Number, Cylinder High/Low, H n/a.
SRV
7 6 5 4 3 2 1 0
- - - - - - - -
V V V V V V V V
V V V V V V V V
V V V V V V V V
V V V V V V V V
V V V V V V V V
1 L 1 D H H H H
1 1 0 0 1 1 0 0
Error Register
4 3 2 1
IDN 0 ABT T0N AMN
V 0 V 0
The number of sectors to be transferred low order. A value of 00h indicates that
256 sectors are to be transferred.
Bits 7-3 (Tag) contain the Tag for the command being delivered.
Starting sector number or LBA address bits 7-0.
Starting cylinder number or LBA address bits 23-:8.
Starting head number or LBA address bits 27-24.
Bits 7 - 3 (Tag) contain the Tag of the command being bus released.
Bit 2 (REL) is set to one.
Bit 1 (I/O) is cleared to zero.
Bit 0 (C/D) is cleared to zero.
Cleared to zero when the device performs a bus release. This bit is set to 1 when
the device is ready to transfer data.
Deskstar 7K400 Hard Disk Drive Specification
Command Block Input Registers
Register
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Status
0 7 6
BSY RDY DF DSC DRQ
0 0 V
228
7 6 5 4 3 2 1 0
- - - - - - - -
see below
V V V V V V V V
V V V V V V V V
V V V V V V V V
V V V V V V V V
- - - - H H H H
see below
Status Register
5 4 3 2
COR IDX
0 V - 0
1 0
ERR
- V