6.7 Multi word DMA timings
The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description.
Table 24: Multiword DMA cycle timing chart
CS0-/CS1-
DMARQ
DMACK-
DIOR-/DIOW-
READ DATA
WRITE DATA
Table 25: Multiword DMA cycle timings
PARAMETER DESCRIPTION
t0
Cycle time
tD
DIOR-/DIOW- asserted pulse width
tE
DIOR- data access
tF
DIOR- data hold
tG
DIOR-/DIOW- data setup
tH
DIOW- data hold
tI
DMACK- to -DIOR-/DIOW- setup
tJ
DIOR-/DIOW- to DMACK- hold
tKR/tKW DIOR-/DIOW- negated pulse width
tLR/tLW DIOR-/DIOW- to DMARQ- delay
tM
CS (1:0) valid to DIOR-/DIOW-
tN
CS (1:0)
tZ
DMACK- to read data released
tM
t0
tI
tD
tG
tE
tH
tG
Deskstar 7K400 Hard Disk Drive Specification
34
tLR/tLW
tKR/tKW
tF
MIN (ns)
120
70
–
5
20
10
0
5
25
–
25
10
–
tN
tJ
tZ
MAX (ns)
–
–
50
–
–
–
–
–
–
35
-
-
25