Multi Word Dma Timings; Table 27: Multiword Dma Cycle Timings - Hitachi HTS548040M9AT00 Specifications

7.8 Multi word DMA timings

The Multi word DMA timings meet Mode 2 of the ATA/ATAPI-6 description.
DMARQ
DMACK-
DIOR-/DIOW-
READ DD(15:0)
WRITE DD(15:0)

Table 27: Multiword DMA cycle timings

PARAMETER DESCRIPTION
t0 Cycle time
tD DIOR-/DIOW- asserted pulse width
tE DIOR- data access
tF DIOR- data hold
tG DIOR-/DIOW- data setup
tH DIOW- data hold
tI DMACK- to DIOR-/DIOW- setup
tJ DIOR-/DIOW- to DMACK- hold
tKR/tKW DIOR- negated pulse width / DIOW- negated pulse width
tLR/tLW DIOR- to DMARQ delay / DIOW- to DMARQ delay
tZ DMACK- to read data released
tLR/tLW
t0
tI tKR/tKW
tD
tG
tG
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tF
tH
MIN (ns)
120
tJ
tZ
MAX (ns)
–
70 –
– 50
5 –
20 –
10 –
0 –
5 –
25 –
– 35
– 25