Multiword Dma Timings; Table 23. Multiword Dma Cycle Timing Chart; Table 24. Multiword Dma Cycle Timings - Hitachi HDS725050KLA360 Specifications

6.7 Multiword DMA timings

The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description.
Table 23: Multiword DMA cycle timing chart
CS0-/CS1-
DMARQ
DMACK-
DIOR-/DIOW-
READ DATA
WRITE DATA
Table 24: Multiword DMA cycle timings
PARAMETER DESCRIPTION
t0 Cycle time
tD DIOR-/DIOW- asserted pulse width
tE DIOR- data access
tF DIOR- data hold
tG DIOR-/DIOW- data setup
tH DIOW- data hold
tI DMACK- to -DIOR-/DIOW- setup
tJ DIOR-/DIOW- to DMACK- hold
tKR/tKW DIOR-/DIOW- negated pulse width
tLR/tLW DIOR-/DIOW- to DMARQ- delay
tM CS (1:0) valid to DIOR-/DIOW-
tN CS (1:0)
tZ DMACK- to read data released
tM
tI tD
tE
tG
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tLR/tLW
t0
tKR/tKW
tG tF
tH
34
tN
tJ
tZ
MIN (ns) MAX (ns)
120 –
70 –
– 50
5 –
20 –
10 –
0 –
5 –
25 –
– 35
25 -
10 -
– 25