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3.3 Internal Clock
Serial BERT 12.5 Gb/s User Guide
The internal clock is generated from a low-frequency (LF) 1/16th-rate clock
signal that is multiplied up to the high-frequency (HF) clock rate, 9.85 to
11.35 GHz. The internal HF clock or an external 500 MHz to 12.5 GHz clock is
required to trigger the PRBS generator and error detector. The generator and
detector operate at 1 bit per clock cycle (10 Gb/s at a clock speed of 10 GHz).
Figure 5. N4962A block diagram – internal clock system
The internal LF 1/16th-rate clock can be phase locked to an external source in
order to synchronize the N4962A with the external device. To synchronize the
clocks, follow the procedure detailed below. The internal or external LF clock is
available from the buffered LF TrigO connector.
System Details and Performance Specifications
27
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