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Fujitsu CS90A User Manual

130nm node cmos process (cs90a).
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130nm node CMOS Process (CS90A)
Features
Technology Code
Transistor
Physical Gate Length (nm)
Gate Oxide Thickness (nm)
Supply Voltage (V)
NMOS Ids (µA/µm)
PMOS Ids (µA/µm)
NMOS Ioff (nA/µm)
PMOS Ioff (nA/µm)
Gate Leak Current (nA/µm)
Basic Gate Delay (ps)
Number of Available Poly Layer
Number of Available Metal Layer
Via Filling
ILD Structure
SRAM Cell Size (µm2)
Dual Gate Oxide Options
Mixed Signal Options
RF Elements
Fuse
Technology Roadmap
1000
500
200
100
50
20
G: Generic, LL: Low Leakage
10
1998
CS90A
UHS
HS
110
110
2.9
2.9
1.2
1.2
780
678
-321
-276
36
4
-18
-3.1
0.01
0.01
14
17
8Cu+1Al
Cu Dual Damascene
Hybrid Low-k
1.98
Available
Available
MIM cap., Poly Resistor, Inductor
RAM Redundancy
180-nm
130-nm
Cu
90-nm
Cu+Low+k
Cu+VLK
CS80/80A
CS90A
CS100A_LL
CS90
CS100A_G
CS100
For COT
CS200
2000
2002
2004
Year (Production Start)
ST
LL
110
110
2.9
2.9
1.2
1.2
570
390
-218
-150
0.18
0.005
-0.22
-0.015
0.01
0.01
28
45
1
65-nm
45-nm
32-nm
For ASIC & COT
CS200A_LL
CS200A_G
2006
2008
2010
Mie plant
2012

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   Summary of Contents for Fujitsu CS90A

  • Page 1

    130nm node CMOS Process (CS90A) Features Technology Code Transistor Physical Gate Length (nm) Gate Oxide Thickness (nm) Supply Voltage (V) NMOS Ids (µA/µm) PMOS Ids (µA/µm) -321 NMOS Ioff (nA/µm) PMOS Ioff (nA/µm) Gate Leak Current (nA/µm) 0.01 Basic Gate Delay (ps)

  • Page 2

    130nm node CMOS Process (CS90A) Transistor Interconnect FUJITSU MICROELECTRONICS AMERICA, INC. Corporate Headquarters 1250 E. Arques Ave. Sunnyvale, CA 94088-3470 Tel: (800) 866-8608 Fax: (408) 737-5999 E-mail: inquiry@fma.fujitsu.com Web Site: http://www.fma.fujitsu.com SiLK SiO2 SRAM 1.65µm Cell Size = 1.98µm (1.2µm x 1.65µm)

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