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BV34.
Processor May Fail to Acknowledge a TLP Request
Problem:
When a PCIe root port's receiver is in Receiver L0s power state and the port initiates a
Recovery event, it will issue Training Sets to the link partner. The link partner will
respond by initiating an L0s exit sequence. Prior to transmitting its own Training Sets,
the link partner may transmit a TLP (Transaction Layer Packet) request. Due to this
erratum, the root port may not acknowledge the TLP request.
Implication:
After completing the Recovery event, the PCIe link partner will replay the TLP request.
The link partner may set a Correctable Error status bit, which has no functional effect.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV35.
An Unexpected PMI May Occur After Writing a Large Value to
IA32_FIXED_CTR2
Problem:
If the fixed-function performance counter IA32_FIXED_CTR2 MSR (30BH) is configured
to generate a performance-monitor interrupt (PMI) on overflow and the counter's value
is greater than FFFFFFFFFFC0H, then this erratum may incorrectly cause a PMI if
software performs a write to this counter.
Implication:
A PMI may be generated unexpectedly when programming IA32_FIXED_CTR2. Other
than the PMI, the counter programming is not affected by this erratum as the
attempted write operation does succeed.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV36.
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in
Certain Conditions
Problem:
Under specific internal conditions, if software tries to write the IA32_FIXED_CTR1 MSR
(30AH) a value that has all bits [31:1] set while the counter was just about to overflow
when the write is attempted (i.e. its value was 0xFFFF FFFF FFFF), then due to this
erratum the new value in the MSR may be corrupted.
Implication:
Due to this erratum, IA32_FIXED_CTR1 MSR may be written with a corrupted value.
Workaround:
Software may avoid this erratum by writing zeros to the IA32_FIXED_CTR1 MSR,
before the desired write operation.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV37.
PCIe* LTR Incorrectly Reported as Being Supported
Problem:
LTR (Latency Tolerance Reporting) is a new optional feature specified in PCIe rev. 2.1.
The processor reports LTR as supported in LTRS bit in DCAP2 register (bus 0; Device 1;
Function 0; offset 0xc4), but this feature is not supported.
Implication:
Due to this erratum, LTR is always reported as supported by the LTRS bit in the DCAP2
register.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
30
Specification Update
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