Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 51
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Status:
For the steppings affected, see the Summary Tables of Changes.
AAO107.
Multiple ECC Errors May Result in Incorrect Syndrome Being Logged
Problem:
When multiple correctable DRAM ECC errors occur the processor may log the syndrome
of a previous error or may log an unknown value.
Implication:
Due to this erratum, the value logged in the IA32_MCi_MISC MSR will not correspond
to the most recent error.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO108.
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
Problem:
A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the
Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error
code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status
register.
Implication:
Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate
indication of multiple occurrences of DTLB errors. There is no other impact to normal
processor functionality.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO109.
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
Problem:
When a debug exception is signaled on a load that crosses cache lines with data
forwarded from a store and whose corresponding breakpoint enable flags are disabled
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.
Implication:
The debug exception DR6.B0-B3 flags may be incorrect for the load if the
corresponding breakpoint enable flag in DR7 is disabled.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO110.
An Exit From the Core C6-state May Result in the Dropping of an
Interrupt
Problem:
In a complex set of internal conditions when the processor exits from Core C6 state, it
is possible that an interrupt may be dropped.
Implication:
Due to this erratum, an interrupt may be dropped. Intel has not observed this erratum
with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO111.
PCIe Extended Capability Structures May be Incorrect
Problem:
The PCIe Extended Capability structure at Offset 0x100 of Bus 0; Devices 0, 3, 4, 5 and
6 contains a Capability ID of AER (Advanced Error Reporting), but these devices do not
support AER. The Next Capability Offset field of this Extended Capability structure
contains 0x150 which is the offset of the next Extended Capability structure. For Bus 0;
Devices 4, 5, and 6, the Next Capability Offset field of the Extended Capability
structure at offset 0x150 should contain 0 to indicate the end of the capability chain but
Specification Update
51
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