Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 48
Specification update
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AAO96.
Multiple Performance Monitor Interrupts are Possible on Overflow of
Fixed Counter 0
Problem:
The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs.
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and
counter are configured as follows:
• Intel® Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = '0)
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = '1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = '1)
Implication:
When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows
Workaround:
Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H) bit
[12].
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO97.
SVID and SID of Devices 8 and 16 only implement bits [7:0]
Problem:
Bits [15:8] of SVID (Subsystem Vendor ID, Offset 2CH) and the SID (Subsystem
Device ID, Offset 2EH) of devices 8 and 16 are not implemented. Only the lower bits
[7:0] of these registers can be written to, though the PCI-e specification indicates that
these are 16-bit registers.
Implication:
Only bits [7:0] of SVID and SID can be written. Bits [15:8] will always be read as 0.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO98.
No_Soft_Reset Bit in the PMCSR Does Not Operate as Expected
Problem:
When the No_Soft_Reset bit in the Power Management Control and Status Register
(PMCSR; Bus 0; Devices 0, 3, 4, 5; Function 0; Offset 0xE4; Bit 3) is cleared the device
should perform an internal reset upon transitioning from D3
erratum the device does not perform an internal reset upon transitioning from D3
D0.
Implication:
When the No_Soft_reset bit in the PMCSR register is set or cleared no internal reset of
the device will be preformed when transitioning from D3
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
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