Time Base Generator Circuit - Fujitsu MPE3XXXAT Product Manual

(2) Programmable filter
The programmable filter circuit has a low-pass filter function that eliminates unnecessary high
frequency noise component and a high frequency boost-up function that equalizes the
waveform of the read signal.
Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in
read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the
cut-off frequency and boost-up gain according to the transfer frequency of each zone.
(3) Adaptive equalizer circuit
This circuit is 5-tap sampled analog transversal filter circuit that cosine-equalizes the head read
signal to the Extended Partial Response Class 4 (EPR4) waveform.
(4) Viterbi detection circuit
The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi
detection circuit. The Viterbi detection circuit demodulates data according to the survivor
path sequence.
(5) Data separator circuit
The data separator circuit generates clocks in synchronization with the output of the adaptive
equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the
clock signals from a synthesizer.
(6) 16/17 GCR decoder
This circuit converts the 17-bits read data into the 16-bits NRZ data.
4.6.4

Time base generator circuit

The drive uses constant density recording to increase total capacity. This is different from the
conventional method of recording data with a fixed data transfer rate at all data area. In the
constant density recording method, data area is divided into zones by radius and the data
transfer rate is set so that the recording density of the inner cylinder of each zone is nearly
constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.2
describes the data transfer rate and recording density (BPI) of each zone.
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