Timing; Table 18: Pcm Timingp; Figure 13: Pcm Timingd - Wavecom CM52 Integrator's Manual

2.6.1.2

Timing

Timing shall be according to the following diagram (see Figure 13: PCM Timing Diagram). The
signals in the diagram shall be interpreted according to the following relation.
The meaning and value of the timing parameters are described in Table 18.
Name
t
SYNC
t
SYNCA
t
SYNCD
t
SU(SYNC)
t
H(SYNC)
t
CLK
t
CLKH
t
CLKL
t
PDLD
T
SU(ULD)
T
H(ULD)
CM52 Integrators' Manual
WI_DEV_CM52_UGD_001-001
Page 29 of 53
Description
PCM_SYNC cycle time.
PCM_SYNC frequency
PCM_SYNC asserted time.
PCM_SYNC de-asserted time.
PCM_SYNC setup time to PCM_CLK
rising.
PCM_SYNC hold time after PCM_CLK
falling.
PCM_CLK cycle time.
PCM_CLK frequency
PCM_CLK high time.
PCM_CLK low time.
Propagation delay from PCM_CLK
rising to PCM_DLD valid.
PCM_ULD setup time to PCM_CLK
falling.
PCM_ULD hold time after PCM_CLK
falling.
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à des tiers sans son autorisation préalable
Figure 13: PCM Timing Diagram
Min
62.4
62.4
1.95
1.95
3.8
3.8
70
20
Table 18: PCM Timing Parameters
CM52 Integrators' Manual
Typical Max Unit
125 Us
8.0 kHz
62.5 Us
62.5 Us
us
us
7.8 us
128 kHz
3.9 us
3.9 us
50 ns
ns
ns