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A
X
4
B
-
5
3
3
P
l
u
s
A
X
4
B
-
5
3
3
P
l
u
s
D
M
A
(
D
i
r
e
c
t
M
e
m
o
D
M
A
(
D
i
r
e
c
t
M
e
m
o
Channel for communications between the memory and surrounding devices.
E
E
C
C
C
C
(
(
E
E
r
r
r
r
o
o
r
r
C
C
h
h
e
e
c
c
k
k
i
i
The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
E
E
D
D
O
O
(
(
E
E
x
x
t
t
e
e
n
n
d
d
e
e
d
d
D
D
a
a
The EDO DRAM technology is actually very similar to FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory
output data to start the pre-charge activity, EDO DRAM holds the memory data valid until the next memory access cycle, that is
similar to pipeline effect and reduces one clock state.
E
E
E
E
P
P
R
R
O
O
M
M
(
(
E
E
l
l
e
e
c
c
t
t
r
r
o
o
n
n
2
Also known as E
PROM. Both EEPROM and
technology is different. Size of EEPROM is much smaller than flash ROM.
r
y
A
c
c
e
s
s
)
r
y
A
c
c
e
s
s
)
n
n
g
g
a
a
n
n
d
d
C
C
o
o
r
r
r
r
e
e
c
c
t
t
i
i
o
o
n
n
t
t
a
a
O
O
u
u
t
t
p
p
u
u
t
t
)
)
M
M
e
e
m
m
o
o
r
r
y
y
i
i
c
c
E
E
r
r
a
a
s
s
a
a
b
b
l
l
e
e
P
P
r
r
o
o
g
g
r
r
a
a
Flash ROM
)
)
m
m
m
m
a
a
b
b
l
l
e
e
R
R
O
O
M
M
)
)
can be re-programmed by electronic signals, but the interface
114
O
n
l
i
n
e
M
a
n
u
a
l
O
n
l
i
n
e
M
a
n
u
a
l
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