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Parallel input connector port
Pin No.
Return pin No.
1
19
2
20
DATA1 (LSB)
3
21
4
22
5
23
6
24
7
25
8
26
9
27
DATA8 (MSB)
10
28
11
29
12
13
14
16•17
18
19 - 30
16
31
Reverse Request
32
Periph Request
15•
33 - 35
36
Signal allocation (Signal : ECP)
Signal
From/To
HostClk
PC/VCP
PC/VCP
DATA2
PC/VCP
DATA3
PC/VCP
DATA4
PC/VCP
DATA5
PC/VCP
DATA6
PC/VCP
DATA7
PC/VCP
PC/VCP
PeriphClk
PC/VCP
PeriphAck
PC/VCP
AckReverse
PC/VCP
PC/VCP
Xflag
HostAck
PC/VCP
GND
High
PC/VCP
GND
PC/VCP
PC/VCP
PC/VCP
NC
1284 Active
PC/VCP
Forward data transfer : Becomes "Low" when PeriphAck is "Low"
and there is data to be read. Returns to "High" when PeriphACK
becomes "High".
High: data 1
Low: data 0
Information will be expressed for parallel data of every signal from
bit No.1 to No.8.
Reverse data transfer : Sends "Low" data when HostAck is "Low".
Returns to "High" when HostAck becomes "High".
Forward data transfer :
High : VCP is on BUSY status.
Low : VCP can accept data.
High: Forward data transfer (Receive)
Low : Reverse data transfer (Send)
High : During supporting ECP mode
Reverse data transfer :
High : PC is on BUSY status.
Low : PC can send data.
Earth
PeripheralLogicHigh
Earth
Low : When PC requests VCP to send data
Low : When VCP requests PC to send data
Unused
Becomes "High" when VCP requests each mode of IEEE1284.
Function
13
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