Details Of Chipset Features Setup - Intel YM430TX User Manual

Details of Chipset Features Setup

Auto Configuration (60ns DRAM)
The default setting of 60ns DRAM sets the optimal timings for items 2
through 9 for 60ns DRAM modules. If you are using 70ns DRAM
modules, you must change this item to 70ns DRAM. The Disabled setting
enables you to set the timings for items 2 through 9.
SDRAM CAS# Latency (3T)
The YM430TX motherboard and chipset support CAS# latency of either
2 or 3 clocks. Check the CAS# latency specification in the datasheet for
the DIMMs you are using. If the DIMMs support a 2-clock CAS# latency,
you can set this to 2T for better performance. Otherwise, leave this setting
at the default (3T).
SDRAM Speculative Read (Disabled)
If this feature is Enabled, the CPU will issue predict commands to access
the DRAM. If a miss occurs, the CPU will cancel the command. Some
operating systems under certain situations have a problem utilizing this
feature so it is normally Disabled.
Passive Release (Enabled)
This feature allows concurrency of ISA/EISA cycles and CPU-to-PCI
cycles. When this feature is enabled, the TXC will be possible to re-
arbitrate PCI bus and allow the CPU to access PCI even when the PCEB
has been granted the bus.
Delayed Transaction (Disabled)
If Enabled, this feature frees the PCI Bus during CPU accessing of 8-bit
ISA cards, which normally consume about 50-60 PCI Clocks without PCI
delayed transaction. If PCI Bus Masters cannot use the PCI Bus, leave
this on the default setting of Disabled for some ISA cards that are not PCI
2.1 compliant.
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