Advanced Chipset Features - Intel MB896 User Manual

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.
DRAM Timing Selectable
CAS Latency Time
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
Precharge delay (tRAS)
System Memory Frequency
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole at 15M-16M
PCI Express Root Port Func
** On-Chip VGA Setting **
PEG/On Chip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED memory Size
Boot Display
Panel Scaling
Panel Number
TV Standard
Video Connector
TV Format
Onboard PCU-E LAN
LAN PXE Option ROM
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The
system board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
4
4
4
12
533MHZ
1 to 2 Sec
Enabled
Disabled
Disabled
Press Enter
Auto
8MB
DVMT
128MB
Auto
Auto
1024x768 18 bit SC
Off
Automatic
Auto
Enable
All Disable
MB896 User' s Manual
BIOS SETUP
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