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Defines the interrupt latch bit position.
2
Defines the adapter failure bit position.
3
Defines the transmit complete bit position.
4
Defines the transmit available bit position.
5
Defines the receive complete bit position.
6
Defines the receive early bit position.
7
Defines the interrupt request bit position.
8
Defines the update statistics bit position.
9
Defines the command in-progress bit position.
10
Defines the current window number bit position.
11
2.2 Command Port Register Offset Definitions
The following code shows the offset definitions for the command port
register. Bits 0:10 contain optional parameter bits and bits 11:15 contain
the command.
#define CMD_PORT
#define CMD_RESET
#define CMD_WINDOW0
#define CMD_WINDOW1
#define CMD_WINDOW2
#define CMD_WINDOW3
#define CMD_WINDOW4
#define CMD_WINDOW5
#define CMD_WINDOW6
#define CMD_START2
#define CMD_RXDIS
#define CMD_RXENA
#define CMD_RXRESET
#define CMD_RXDTP
#define CMD_TXENA
#define CMD_TXDIS
#define CMD_TXRESET
#define CMD_REQINT
#define CMD_ACKINT
#define CMD_SINTMASK
#define CMD_ZINTMASK
#define CMD_FILTER
enum rx_filter {
RF_IND
=0x1,
RF_GRP
=0x2,
RF_BRD
=0x4,
RF_PRM
=0x8
};
#define CMD_RXEARLY
#define CMD_TXAVAILTHRESH
#define CMD_TXSTARTTHRESH
#define CMD_STATSENA
#define CMD_STATSDIS
#define CMD_STOP2
#define CMD_RXRECTHRESH
2–2 Defining Device Register Offsets
0xe
1
(0x0)
2
((0x1<<11)+0x0)
((0x1<<11)+0x1)
((0x1<<11)+0x2)
((0x1<<11)+0x3)
((0x1<<11)+0x4)
((0x1<<11)+0x5)
((0x1<<11)+0x6)
(0x2<<11)
10
(0x3<<11)
11
(0x4<<11)
12
(0x5<<11)
13
(0x8<<11)
14
(0x9<<11)
15
(0xa<<11)
16
(0xb<<11)
17
(0xc<<11)
18
(0xd<<11)
19
(0xe<<11)
20
(0xf<<11)
21
(0x10<<11)
22
23
(0x11<<11)
24
(0x12<<11)
25
(0x13<<11)
26
(0x15<<11)
27
(0x16<<11)
28
(0x17<<11)
29
(0x18<<11)
30
3
4
5
6
7
8
9
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