Dram Configuration - DFI LanParty UT CFX3200-DR User Manual

3
BIOS Setup

DRAM Configuration

Move the cursor to this field and press <Enter>. The following
screen will appear.
↑↓→←
F5: Previous Values
The screen above list all the fields available in the DRAM Configuration submenu,
for ease of reference in this manual. In the actual CMOS setup, you have to use
the scroll bar to view the fields. The settings on the screen are for reference only.
Your version may not be identical to this one.
DRAM Frequency Set (Mhz)
This field is used to set a memory clock limit on the system. This will
prevent the memory speed from running faster than this frequency.
Command Per Clock (CPC)
This field is used to enable the DRAM commands and address that
will be driven for 2 clock cycles and select the second phase of the
2 clock command and address.
108
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Frequency Set (MHz)
Command Per Clock (CPC)
CAS Latency Control (Tcl)
RAS# to CAS# Delay (Trcd)
Min RAS# Active Time (Tras)
Row Precharge Time (Trp)
Row Cycle Time (Trc)
Row Refresh Cyc Time (Trfc)
Row to Row Delay (Trrd)
Write Recovery Time (Twr)
Write to Read Delay (Twtr)
Read to Write Delay (Trwt)
Refresh Period (Tref)
DRAM Bank Interleaving
DQS Skew Control
DQS Skew Value
DRAM Drive Strength
DRAM Data Drive Strength
Skew Control A
Skew Control B
Buttom of 32-bit[31:24] IO
Max Async Latency
Read Preamble Time
Idle Cycle Limit
Dynamic Counter
R/W Queue Bypass
Bypass Max
32 Byte Granularity
Burst Length
: Move Enter: Select
DRAM Configuration
By DRAM SPD Value
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Enabled
Auto
0
Auto
Auto
Auto
Auto
E0
Auto
Auto
Auto
Auto
Auto
Auto
Auto
4 beats
+/-/PU/PD: Value F10: Save
F6: Fail-Safe Defaults
Item Help
Menu Level
ESC: Exit F1: General Help
F7: Optimized Defaults