Pcie Configuration - DFI LanParty UT CFX3200-DR User Manual

PCIE Configuration

Move the cursor to the South Configuration field and press <Enter>.
The following screen will appear.
Link Width ............................GFX1
............................GFX1
Payload Size......................... GFX
..........................SB
Lane Reversal.......................GFX1
PowerDown Unused Port
Hide Empty PCIE Port
Reset GFX Slot
Reset GFX2 Slot
Reset GPP Slots
Delay After PCIE Reset (mS)
GFX Card WorkAround
TXCLK Gating
P2P Write Between GFX1/2
PCIE Common Clock
ASPM L1.............................. GFX
.............................. GPP
.............................. SB
10% Extra Current................GFX1
↑↓→←
: Move Enter: Select
F5: Previous Values
The settings on the screen are for reference only. Your version may not be
identical to this one.
Link Width GFX1
The options are x1, x2, x4, x8, x12 and x16.
Payload Size GFX/SB
This field is used to select the payload size of the PCI Express
devices. The unit is byte.
Lane Reversal GFX1/GFX2
The options are Enabled and Disabled.
Power Down Unused Port GFX1/GPP
The options are Enabled and Disabled.
Hide Empty PCIE Port
The options are Enabled and Disabled.
Phoenix - AwardBIOS CMOS Setup Utility
PCIE Configuration
x16
x16
64 Bytes
64 Bytes
Disabled
.......................GFX2 Disabled
GFX1 Enabled
GPP Enabled
Enabled
Enabled
Enabled
Enabled
0
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
................GFX2 Disabled
................GPP Disabled
................SB Disabled
+/-/PU/PD: Value
F6: Fail-Safe Defaults
BIOS Setup
Item Help
Menu Level
F10: Save ESC: Exit F1: General Help
F7: Optimized Defaults
3
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