Chipset Overview - Supermicro Supero X8DTU-F User Manual

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Chipset Overview

Built upon the functionality and the capability of the Intel 5520 platform, the
X8DTU/X8DTU-F motherboard provides the performance and feature set required
for dual-processor-based high-end systems with configuration optimized for HPC/
Cluster servers and intensive applications. The 5520 platform consists of the
5500/5600 Series (LGA 1366) processor, the 5520 (IO Hub), and the ICH10R
(South Bridge). With the Intel QuickPath interconnect (QPI) controller built in, the
5500/5600 Series Processor is the first dual-processing platform that offers the
next generation point-to-point system interconnect interface greatly enhancing
system performance by utilizing serial link interconnections, allowing for increased
bandwidth and scalability.
The IOH connects to each processor through an independent QuickPath Intercon-
nect (QPI) link. Each link consists of 20 pairs of unidirectional differential lanes
for data transmission in addition to a differential forwarded clock. A full-width QPI
link pair provides 84 signals. Each processor supports two QuickPath links, one
going to the other processor and the other to the 5520 North Bridge.
The 5520 chipset supports up to 36 PCI Express Gen2 lanes, peer-to-peer read
and write transactions. The ICH10R provides up to 6 PCI-Express ports, six SATA
ports and eight USB connections.
In addition, the 5520 chipset also offers a wide range of RAS (Reliability, Availabil-
ity and Serviceability) features. These features include memory interface ECC, x4/
x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC), parity
protection, out-of-band register access via SMBus, memory mirroring, memory
sparing, and Hot-plug support on the PCI-Express Interface.
Main Features of the 5500/5600 Series Processor and the
5520 Chipset
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Four processor cores in each processor with 8MB shared cache among cores
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Two full-width Intel QuickPath interconnect (QPI) links, up to 6.4 GT/s of data
transfer rate in each direction
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Virtualization Technology, Integrated Management Engine supported
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Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and
Concurrent bi-directional traffic
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Error detection via CRC and Error correction via Link level retry
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Chapter 1: Introduction