The Sis 5595 Pci/Isa Bridge Chip - HP Vectra VEi7 Technical Reference Manual

Chip Sets
DRAM (Main Memory)
The DRAM controller supports two DIMM slots. The maximum system
memory size supported is 512MB. The memory clock frequency can be
Controller
operated at up to 100MHz and can be in synchronous or asynchronous
modes with respect to host bus frequency. The host/DRAM clock
scheme is 66/66MHz.
IDE Controller
The PCI master/slave IDE controller supports four devices, two on each
of two channels.
Read/Write Buffers
The SiS 620 chip defines a data buffering scheme to support the
required level of concurrent operations and provide adequate sustained
bandwidth between the DRAM subsystem and all other system
interfaces (Host, AGP and PCI).
System Clocking
The SiS 620 chip operates the host interface at 66 MHz, the
SDRAM/core at 66 MHz, PCI at 33 MHz and AGP at 66 MHz. Coupling
between all interfaces and internal logic is done in a synchronous
manner. The clocking scheme uses an external clock synthesizer (which
produces reference clocks for the host and PCI interfaces).

The SiS 5595 PCI/ISA Bridge Chip

The SiS 5595 chip is a multi-function PCI device implementing a PCI-
to-ISA bridge function, a PCI IDE function, a Universal Bus host/hub
function, and an Enhanced Power Management function.
The following figure shows an example of the system block diagram
using the SiS 5595 chip.
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Core Components and Technologies