The Piix4E Pci/Isa Bridge Chip (82371Eb) - HP Vectra VEi7 Technical Reference Manual

Read/Write Buffers
The 440ZX chip defines a data buffering scheme to support the required
level of concurrent operations and provide adequate sustained
bandwidth between the DRAM subsystem and all other system
interfaces (Host, AGP and PCI).
System Clocking
The 440ZX chip operates the host interface at 100MHz, the
SDRAM/core at 100MHz, PCI at 33 MHz and AGP at 66 MHz. Coupling
between all interfaces and internal logic is done in a synchronous
manner. The clocking scheme uses an external clock synthesizer (which
produces reference clocks for the host and PCI interfaces).

The PIIX4E PCI/ISA Bridge Chip (82371EB)

The universal host controller interface (UHCI) chip, known as PIIX4E,
is encapsulated in a Ball Grid Array (BGA) package.
The PIIX4E chip is a multi-function PCI device implementing a PCI-to-
ISA bridge function, a PCI IDE function, a Universal Bus host/hub
function, and an Enhanced Power Management function.
Core Components and Technologies
Chip Sets
13