Data Path Unit (82438Fx); The Pci/Isa Bridge And Ide Controller (82371Fb) - HP Vectra VL5 4 Technical Reference Manual

Function
DRAM controller
PCI slave interface
PCI master interface
PCI bus arbiter
*The Pentium's internal cache has a 32-byte line size, which is four times the width of the Pentium's
host data bus. Burst reads and writes by the Pentium involve a full cache line, and so require four
back-to-back cycles to complete. The first cycle in each burst of four always requires more time to
complete than the three subsequent cycles. This is because the first cycle includes the addressing
phase and precharge timing (for memory).

DATA PATH UNIT (82438FX)

The 82438FX component contains a 64-bit data path between the host bus and main memory.
A 4×64-bit deep buffer provides 3-1-1-1 writes to main memory.
This buffer is used for:
• writes from processor to main memory
• level-two cache write back cycles
• transfers from PCI to main memory.

THE PCI/ISA BRIDGE AND IDE CONTROLLER (82371FB)

The 82371FB device serves as a bridge between the PCI bus and the ISA expansion bus, and
incorporates a two-channel PCI IDE controller. It incorporates the logic for a PCI interface, a
DMA interface, a DMA controller that supports fast DMA transfers, data buffers to isolate the
PCI and ISA buses, Timer/Counter logic, and NMI control logic.
Features
• Uses dedicated DRAM memory address and data buses
• Page mode - one or two pages open simultaneously
• Supports pipelined accesses
• Full RAS/CAS programmability
• Flexible bank configurations (each bank programmable for DRAM
size, bank width and single or double-sided modules)
• Self configuring bank start addresses
• Shadow RAM support for the memory region 640 KB -
1 MB (in 16 KB segments)
• System management memory support
• RAS only refresh
• Fast memory access 7-2-2-2* with Extended Data Out (EDO) memory
• Becomes processor (local) bus master to generate DRAM
requests on behalf of other PCI bus masters
• Supports PCI bus burst cycles
• Supports posted writes to DRAM for PCI burst writes
• Supports read-ahead from DRAM for PCI burst reads
• Provides for programmable PCI bus memory regions in
memory address map
• Supports PCI bus burst cycles for 64-bit and 32-bit misaligned Pentium
reads and writes
• Optional posting of PCI memory and I/O writes
• Optional buffering of PCI memory writes
• Optional read-ahead for processor to PCI accesses
• Supports PCI bus arbitration for up to four masters
• Supports rotating priority scheme