Server Topology; Dual-Simplex Lanes - HP BL680c - ProLiant - G5 Introduction Manual

Server topology

The PCI Express architecture (Figure 2) provides unidirectional point-to-point connections between
devices in two directions (dual-simplex). PCI Express sends the data serially, one bit after another,
over each link rather than sending the data in parallel, one bit beside another, as in PCI-X. Therefore,
PCI Express uses fewer pins.
The PCIe Root Complex shown in Figure 2 is the origin point for all of the native PCIe ports in the
system.
Figure 2. System architecture with PCI Express
CPU
DRAM
Memory Controller
I/O Hub
PCIe Root Complex
x8
x4
RAID Controller
PCIe/PCI-X
x4
Bridge
NIC
x4
x4
PCIe Slots PCI-X 133 Slots

Dual-simplex lanes

A PCI Express serial link consists of one or more dual-simplex lanes. Each lane contains two pairs of
wire conductors (a send differential pair and a receive differential pair) to simultaneously transmit
data at the signaling rate in both directions. The maximum bandwidth of dual-simplex buses is often
specified as the sum of the transmit and receive channels (Figure 3 left). In contrast, PCI-X uses a half-
duplex scheme where the full bus bandwidth is used either to transmit or to receive data (Figure 3
right).
Figure 3. Dual-simplex communication and half-duplex communication
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