Abstract; Introduction; The Parallel Bus System - HP BL680c - ProLiant - G5 Introduction Manual

Abstract

This paper provides an overview of the continuing transition from parallel bus architecture to PCI
Express as well as details on developments that continue to occur within PCI Express. In addition, it
provides an introduction to the new I/O Virtualization technologies that are beginning to be
incorporated into server designs to better support server virtualization solutions that have emerged in
the last several years. It is the goal of HP to continue to support I/O technologies that protect customer
investments and extend I/O performance, flexibility, and reliability

Introduction

There is constant pressure on the Peripheral Component Interconnect (PCI) bus to meet the I/O
bandwidth demands of data traffic traveling between increasingly powerful CPUs and I/O devices.
The PCI standard has continued to meet the needs of CPUs and I/O devices by increasing
performance while maintaining backward compatibility. Historically, local I/O performance on
servers has doubled almost every two years with a new phase of the PCI standard.
With the advent of faster and more complex I/O devices, PCI-X 1.0, which defined device speeds of
PCI-X 66 and PCI-X 133, was introduced to extend the performance and RAS (reliability, availability,
and serviceability) features of PCI technology in servers. PCI-X 1.0 leveraged the wide acceptance of
the PCI bus and doubled the maximum bandwidth to 1066 MB/s with a 64-bit, 133-MHz bus. In
2002, the PCI-SIG extended the PCI-X 1.0 specification with PCI-X 2.0. The PCI-X 2.0 specification is
a smarter, more robust I/O technology that doubles and quadruples PCI-X bandwidth with two
additional device speeds: PCI-X 266 and PCI-X 533.
In 2002, the PCI-SIG also introduced a new physical implementation of PCI, called PCI Express,
which was originally optimized for desktop applications. With bandwidths in excess of 4 GB/s, PCI
Express delivers the performance required for next-generation 10-Gb Ethernet adapters.
This paper begins with a summary of today's parallel bus system and then describes PCI Express
(PCIe) technology, including PCIe 2.0, as well as updating the status of the transition to PCI Express in
HP ProLiant servers. It also provides an introduction to the emerging I/O virtualization technologies
that HP is about to incorporate into server designs in order to enable the next generation Virtual
Machine solutions.

The parallel bus system

The parallel bus system based on PCI or PCI-X standards uses bit-parallel, bi-directional, multi-drop
connections running at relatively low frequency (Figure 1). PCI and PCI-X send 32 or 64 data bits plus
control signals over the parallel bus. The number of pins required corresponds to the width of the bus:
a 32-bit bus requires over 55 pins (data plus control) and a 64-bit bus requires approximately
100 pins.
As the speed of the bus increases, the number of devices that can be shared on a common bus
shrinks. For example:
• 33-MHz PCI supports five or six slots.
• 66-MHz PCI-X supports four slots.
• 100-MHz PCI-X supports two slots.
• 133-MHz and higher PCI-X supports one slot.
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