Chipset; Intel Boxboro I/O Hub (Ioh); Ioh Pci Express (Pcie); Enterprise Southbridge Interface (Esi) - Dell External OEMR R810 Technical Manual

Dell
8

Chipset

7B
The PowerEdge R810 system board incorporates the Intel
interfacing. The 7500 chipset is designed to support Intel
®
family, Intel QPI Interconnect, DDR3 memory technology, and PCI Express Generation 2 (PCIe 2).
The 7500 chipset consists of the IOH QuickPath Interconnect (QPI), Intel
Buffer, and the ICH10 South Bridge.
8.1

Intel Boxboro I/O Hub (IOH)

65B
The R810 system board uses the Intel 7500 series IOH to provide a link between the processor(s) and
I/O components. The main components of the IOH consist of two full-width QuickPath Interconnect
(QPI) links (to processor 1 and 2), 36 lanes of PCI Express Gen2, and a x4 Enterprise Southbridge
Interface (ESI) and an integrated IOxAPIC.
8.2

IOH PCI Express (PCIe)

66B
PCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles the
signaling bit rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are
backwards-compatible with Gen1 transfer rates.
The IOH has 36 PCI Express lanes. The lanes are partitioned as follows:

2 PCI Express Gen2 x2 ports—on-board network controllers

4 PCI Express Gen2 x8 ports—I/O expansion slots
8.3

Enterprise Southbridge Interface (ESI)

67B
The ESI connects the IOH with the Intel I/O Controller Hub ICH10. The ESI is equivalent to a x4 PCIe
Gen1 link with a transfer rate of 1 GB/s in each direction.
8.4

Intel I/O Controller Hub 10 (ICH10)

68B
ICH10 is a highly integrated I/O controller, supporting the following functions:

PCI Bus 32-bit Interface Rev 2.3 running at 33 MHz

Serial ATA (SATA) ports with transfer rates up to 300 MB/s

On the R810, one SATA port for optical devices or tape backup

Six UHCI and two EHCI (high-speed 2.0) USB host controllers, with up to 12 USB ports (R810
uses six of these ports for internal and external use.)

Power management interface (ACPI 3.0b compliant)

Platform Environmental Control Interface (PECI) (The iDRAC controls the PECI interface on
R810, not the ICH10.)

I/O interrupt controller

SMBus 2.0 controller

Low Pin Count (LPC) interface to Super I/O, Trusted Platform Module (TPM), and SuperVU

Serial Peripheral Interface (SPI) support for up to two devices (The R810 BIOS is connected to
the ICH10 using SPI interface.)
Dell PowerEdge R810 Technical Guide
®
7500 chipset for I/O and processor
® ®
Xeon processor 6500 and 7500 series 4S
®
7500 Scalable Memory
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