Memory Ras Support; Sparing; Mirroring; Table 8. Poweredge R810 Sparing And Mirroring - Dell External OEMR R810 Technical Manual

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7.8

Memory RAS Support

62B
The Intel Xeon processor 6500 and 7500 series supports high-availability memory modes including
rank and DIMM sparing as well as memory mirroring. The R810 supports rank sparing only and
mirroring as shown in Table 8.

Sparing

Type
Rules enforced
Rank
The capacity of the spare
rank must be greater
than that of any other
rank on the channel
7.8.1
Sparing
114B
For Rank sparing, one rank on each lockstep Intel 7500 SMB pair will be reserved as a spare, and in
the event that another rank exceeds a threshold of correctable ECC errors, the ―failing‖ rank will be
copied to the spare. Once that operation is complete, the failed rank will be disabled.
7.8.2

Mirroring

115B
For mirroring, the R810 will support 2P/4P configurations with 32 DIMMs only. When mirroring is
enabled, only half of the physical memory will be visible to the system software. A full copy of the
memory is maintained, and in the event of an uncorrectable error, the system will switch over to the
mirrored copy. In 2P mode, the mirroring will be inter-node with hemisphere mode enabled. In this
case, the memory controller (MBox) of CPU1 is mapped to the corresponding MBox of CPU2. The
figure below depicts the mirroring logic for 2P configurations. A, B, C and D represent the DIMM
socket groups.
A
C
For 4-processor configurations, the PowerEdge R810 will also support mirroring in the inter-socket
mode (note that intra-socket is not possible in 4P because each CPU has only one MBox connected to
memory buffers). In this 4P case, the memory on CPU1 will be mirrored with memory on CPU3, while
memory on CPU2 is mirrored with memory on CPU4. Figure 17 depicts the mirroring logic for 2P
configurations. A,B,C and D represent the DIMM socket groups.
Dell PowerEdge R810 Technical Guide

Table 8. PowerEdge R810 Sparing and Mirroring

Mirroring
1P
No support
MBOX0
CPU1
MBOX1

Figure 16. PowerEdge R810 2P Mirroring

2P
4P
Inter-socket
Inter-
(hemisphere
socket
mode
enabled)
MBOX0
CPU2
MBOX1
Rules Enforced
32 DIMM only,
Mirrored must match
D
B
32

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