Agp Function Settings; Pci Timing Settings; Integrated Peripherals - JETWAY PM2M - REV 1.0 User Manual

3-6-2 AGP Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
AGP Share Memory Size
AGP Aperture Size
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Write Buffer
PCI Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.

3-7 Integrated Peripherals

CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
> OnChip IDE Function
> OnChip Device Function
> Onboard Super IO Function
Init Display First
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
AGP Timing Settings
32M
64M
Enabled
Enabled
Enabled
Enabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Enabled
Enabled
F6:Optimized Defaults
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
25
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >
F1:General Help
F7:Standard Defaults