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Feature
NorthBridge Chipset Configuration
Read Write Delay
(Trwt)
Read Preamble
Asynchronous
Latency
3.9.1.1 – Memory Configuration Sub-Menu
This menu has options for memory speed & latency. Use the up and down arrow ( / )
keys to select an item. Use the Plus and Minus (+/-) keys to change the value of the
selected option.
Main
Advanced
Memory Configuration
Memclock Mode
MCT Timing Mode
User Config Mode
Burst Length
SoftWare Memory Hole
HardWare Memory Hole
CPU1 Mem DQ Driver Strength
CPU2 Mem DQ Driver Strength
Option
Bits 6-4. Specifies the read-to-write
delay. This is not a DRAM-specified
timing parameter, but must be
considered due to routing latencies
Read only
on the clock forwarded bus. It is
counted from the first address bus
slot that was not associated with
part of the read burst.
Bits 11-8. The time prior to the max-
read DQS-return when the DQS
receiver should be turned on. This
is specified in units of 0.5ns. The
controller needs to know when to
enable its DQS receiver in
Read only
anticipation of the DRAM DQS driver
turning on for a read. The controller
will disable its DQS receiver until
the read preamble time and then
enable its DQS receiver while the
DRAM asserts DQS.
Bits 3-0. This filed should be loaded
with a 4-bit value equal to the
Read only
maximum asynchronous latency in
the DRAM read round-trip loop.
BIOS Setup Utility
PCI/PnP
Boot
Security
[Auto]
[Auto]
[Auto]
[4 Beats]
[Enabled]
[Enabled]
[No Reduction]
[No Reduction]
58
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Description
Chipset
Exit
MEMCLK can be set
by the code using
AUTO, or if you use
LIMIT, you can set
one of the standard
values.
← → Select Screen
↑↓ Select Item
+/-
Change Option
F1
General Help
F10 Save and Exit
ESC Exit
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