TYAN TEMPEST I5000XT Manual page 43

3.3.3 Advanced Chipset Control
Main Advanced
Advanced Chipset Control
Crystal Beach Configuration
Enable:
SERR signal condition:
4GB PCI Hole Granularity:
Memory Branch Mode:
Branch 0 Rank Interleave:
Branch 0 Rank Sparing:
Branch 1 Rank Interleave:
Branch 1 Rank Sparing:
Enhanced x8 Detection:
Force ITK Config Clocking:
High Precision Event Timer:
Snoop filter:
↑↓
F1 Help Select Item
← →
Esc Exit Select Menu
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None / Single bit / Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If
MTRRs are not enough, we may use this option to reduce the MTRR
occupation.
256MB / 512MB / 1.0GB / 2.0GB
Memory Branch Mode
This option is used to select the type of memory operation mode.
Sequential / Interleave / Mirror / Single Channel 0
Branch 0/1 Rank Sparing
This option is used to enable/disable Branch 0 rank/DIMM sparing feature.
Disabled / Enabled
Enhanced x8 Detection
This feature is used to enable/disable enhanced x8 DRAM UC error detection.
PhoenixBIOS Setup Utility
Security Power
[Disabled]
[Single bit]
[256MB]
[Interleave]
[4:1]
[Disabled]
[4:1]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[Enabled]
-/+ Change Values
Enter Select
Sub-Menu
43
Boot Exit
Item Specific Help
F9 Setup Defaults
F10 Save and Exit