Related Manuals for Cirrus Logic EP9302
Summarization of Contents
Preface
About the EP93xx User’s Guide
Provides an overview of the EP93xx processors and the user guide's scope.
Related Documents from Cirrus Logic
Lists related Cirrus Logic documents for EP93xx processors.
Reference Documents
Lists reference documents for ARM architecture and AMBA specifications.
Notational Conventions
Explains conventions used for signal names, pin names, and register bit fields.
Chapter 1: Introduction
1.1 Introduction
Introduces the EP93xx processors as integrated systems-on-a-chip for various electronic products.
1.2 EP93xx Features
Summarizes EP93xx processors' clock rates, package types, and key features.
1.3 EP93xx Processor Applications
Lists various applications for EP93xx processors, such as media servers, industrial controls, and medical equipment.
1.4 EP93xx Processor Highlights
Highlights key features like ARM920T Core, MaverickCrunch Co-processor, and integrated peripherals.
Chapter 2: ARM920T Core and Advanced High-Speed Bus (AHB)
2.1 Introduction
Describes the ARM920T Core and the Advanced High-Speed Bus (AHB).
2.2 Overview: ARM920T Core
Details the ARM920T core's Harvard architecture, caches, pipeline, and MMU.
2.2.1 Features
Lists key features of the ARM920T core, including instruction sets, AMBA, caches, and MMU.
2.2.2 Block Diagram
Provides a block diagram illustrating the ARM920T core architecture and its components.
Chapter 3: MaverickCrunch Co-Processor
3.1 Introduction
Introduces the MaverickCrunch co-processor for accelerating floating-point and fixed-point arithmetic.
3.1.1 Features
Lists key features of the MaverickCrunch co-processor, such as floating point support and integer operations.
3.1.2 Operational Overview
Explains the MaverickCrunch co-processor's operation via the ARM920T co-processor interface and shared memory.
3.1.3 Pipelines and Latency
Details the MaverickCrunch co-processor's pipelines and their impact on latency and throughput.
Chapter 4: Boot ROM
4.1 Introduction
Introduces the Boot ROM for booting the processor from various devices like SPI Flash or UART1.
4.1.1 Boot ROM Hardware Operational Overview
Describes the Boot ROM as an AHB slave device and its behavior on system reset.
4.1.1.1 Memory Map
Details the Boot ROM's memory map, including aliasing and address space.
4.1.2 Boot ROM Software Operational Overview
Explains the Boot ROM's role in controlling initial off-chip code execution and supported initialization sources.
Chapter 5: System Controller
5.1 Introduction
Introduces the System Controller (Syscon) for clock control, power management, and configuration.
5.1.1 System Startup
Explains the system startup process, including the five categories of reset events.
5.1.2 System Reset
Details the device system reset control levels and events.
5.1.3 Hardware Configuration Control
Describes hardware configuration controls for boot modes, synchronicity, and external boot width.
Chapter 6: Vectored Interrupt Controller
6.1 Introduction
Introduces the Vectored Interrupt Controllers (VIC) for improved interrupt handling.
6.1.1 Interrupt Priority
Explains the interrupt priority levels: FIQ, vectored interrupts, and non-vectored IRQ interrupts.
6.1.2 Interrupt Configuration
Shows Interrupt Configuration table detailing VIC interrupt sources, names, and descriptions.
6.1.3 Interrupt Details
Provides details of interrupts described in Table 6-1, including COMMRX and COMMTX.
Chapter 7: Raster Engine With Analog/LCD Integrated Timing and Interface
7.1 Introduction
Introduces the Raster engine's capability for display timing signals and its support for various display types.
7.2 Features
Lists Raster engine features like pixel blinking, LUTs, frame buffer architecture, and cursor support.
7.3 Raster Engine Features Overview
Provides an overview of Raster engine features, including blinking modes, color generation, and cursor support.
7.4 Functional Details
Details the Raster Engine's video pipeline sections like VILOSATI, FIFO, and pixel MUX.
Chapter 8: Graphics Accelerator
8.1 Overview
Introduces the Graphics Accelerator for improving performance with block copy, fill, and line draw functions.
8.2 Block Processing Modes
Explains block transfer modes including transparency, logical mask, and logical destination operations.
8.2.1 Copy
Describes the copy operation for block transfers, emphasizing disabling of data path options.
8.2.2 Remapping
Explains single bit pixel remapping with foreground/background or transparency.
Chapter 9: 1/10/100 Mbps Ethernet LAN Controller
9.1 Introduction
Introduces the Ethernet LAN Controller, its AHB and MII interfaces, and full duplex operation with flow control.
9.1.1 Detailed Description
Decomposes the Host Interface into AHB Interface Controller and Descriptor Processor.
9.1.1.1 Host Interface and Descriptor Processor
Details the AHB Interface Controller's role in connecting to AHB and serving register programming.
9.1.1.2 Reset and Initialization
Explains the three reset sources for the Ethernet LAN Controller: AHB, software, and channel resets.
Chapter 10: DMA Controller
10.1 Introduction
Introduces the DMA Controller, its interface to peripherals, and memory-to-memory transfers.
10.1.1 DMA Features List
Lists DMA features like programmable channels, buffer descriptors, and interrupt generation.
10.1.2 Managing Data Transfers Using a DMA Channel
Explains how control and status registers manage DMA operations and monitor system interrupts.
10.1.3 DMA Operations
Defines DMA operations by channel type: Memory-to-Memory (M2M) and Memory-to-Peripheral (M2P/P2M).
Chapter 11: Universal Serial Bus Host Controller
11.1 Introduction
Introduces the USB Host Controller, its support for USB 2.0 devices, and compliance with OpenHCI.
11.1.1 Features
Lists USB Host Controller features: OHCI compliance, root hub, and DMA functionality.
11.2 Overview
Presents four focus areas of a USB system: Client Software/USB Driver, HCD, HC, and USB Device.
11.2.1 Data Transfer Types
Defines four USB data transfer types: Interrupt, Isochronous, Control, and Bulk.
Chapter 12: Static Memory Controller
12.1 Introduction
Introduces the Static Memory Controller (SMC) and its support for EP9315 processors regarding PCMCIA.
12.2 Static Memory Controller Operation
Explains SMC operation with various external device types and configurable memory spaces.
12.3 PCMCIA Interface (EP9315 Processor Only)
Details the PCMCIA interface support in the EP9315 processor for PC Cards.
12.4 PC Card Memory-Mode Enable Signals
Explains PC Card memory-mode enable signals (nPC_CE1, nPC_CE2) related to address signals.
Chapter 13: SDRAM, SyncROM, and SyncFLASH Controller
13.1 Introduction
Introduces the SDRAM, SyncROM, and SyncFLASH controller and its features.
13.2 Booting from SyncROM or SyncFLASH
Describes the power-on reset sequence for booting from Synchronous ROM or Synchronous FLASH devices.
13.3 Address Pin Usage
Details the address pin usage for synchronous memory domains and their mapping to external AD[15:0] pins.
13.4 SDRAM Initialization
Provides a general initialization sequence for SDRAM devices.
Chapter 14: UART1 With HDLC and Modem Control Signals
14.1 Introduction
Introduces UART1 as a collection of UART, modem interface, and HDLC blocks.
14.2 UART Overview
Explains UART data transfers managed by DMA, interrupts, or CPU polling.
14.2.1 UART Functional Description
Describes UART functions including serial-to-parallel conversion, Baud Rate generation, and interrupt sources.
14.2.1.1 AMBA APB Interface
Explains the AMBA APB interface for accessing UART registers and FIFO memories.
Chapter 15: UART2
15.1 Introduction
Introduces UART2, its identical UART interface to UART1, and its lack of modem or HDLC interface.
15.2 IrDA SIR Block
Describes the IrDA SIR block containing an Encoder/decoder for serial communication via nSIROUT and SIRIN signals.
15.2.1 IrDA SIR Encoder/decoder Functional Description
Details the IrDA SIR Encoder/decoder components: transmit encoder and receive decoder.
15.2.2 IrDA SIR Operation
Explains IrDA SIR operation modes, including normal and low-power modes, and physical layer specifications.
Chapter 16: UART3 With HDLC Encoder
16.1 Introduction
Introduces UART3, implementing UART and HDLC interfaces, similar to UART1 but without modem interface.
16.2 Implementation Details
Details UART3 package dependency on RXD2, TXD2, and EGPIO[3] pins.
16.2.1 UART3 Package Dependency
Lists UART3 package pins and their control by Syscon register DeviceCfg.
16.2.2 Clocking Requirements
Specifies clocking requirements for PCLK and UARTCLK, including frequency ranges.
Chapter 17: IrDA
17.1 Introduction
Introduces the IrDA module, its compliance with Version 1.1 standard, and support for speeds up to 4 MBit/s.
17.2 IrDA Interfaces
Describes the three IrDA interfaces: Slow Infrared (SIR), Medium Infrared (MIR), and Fast Infrared (FIR).
17.3 Shared IrDA Interface Feature
Covers features common to MIR and FIR interfaces, noting SIR shares enable register and pins with UART2.
17.3.1 Overview
Provides an overview of the Slow Infrared (SIR) Encoder/Decoder, its use of UART2, and data rates.
Chapter 18: Timers
18.1 Introduction
Introduces timers for controlling timed events, including 16-bit, 32-bit, and 40-bit timers.
18.1.1 Features
Lists timer features: two 16-bit timers, one 32-bit timer, and one 40-bit timer.
18.1.2 16 and 32-bit Timer Operation
Explains the operation of TC1, TC2 (16-bit), and TC3 (32-bit) timers, including modes and registers.
18.1.2.1 Free Running Mode
Describes free running mode where counters wrap on underflow.
Chapter 19: Watchdog Timer
19.1 Introduction
Introduces the Watchdog Timer for system-wide reset and recovery reporting.
19.1.1 Watchdog Activation
Explains how to disable or re-enable the Watchdog circuitry via software or hardware signals.
19.1.2 Clocking Requirements
Specifies the nominal frequency of the WATCHDOG_CLK for counter stepping and time-out/reset pulse generation.
19.1.3 Reset Requirements
Lists the four reset inputs for the Watchdog block: HRESETn, USR_RESETn, PWR_RESETn, and RESET_KEYS_DETECTED.
Chapter 20: Real Time Clock With Software Trim
20.1 Introduction
Introduces the Real Time Clock (RTC) and its components: Real Time Clock and RTC TRIM.
20.1.1 Software Trim
Details the RTC oscillator software compensation circuitry for digital calibration.
20.1.1.1 Software Compensation
Explains the generation of the 1 Hz clock using a programmable counter and fractional compensation.
20.1.1.2 Oscillator Frequency Calibration
Describes how manufacturing measures the RTC 32.768 kHz reference clock.
Chapter 21: I2S Controller
21.1 Introduction
Introduces the I2S controller for streaming serial audio data between external CODECs and the ARM Core.
21.2 I2S Transmitter Channel Overview
Details the I2S TX channels, including master/slave mode and data transfer mechanisms.
21.2.1 I2S Transmitter Register Descriptions
Summarizes the register set for the Transmitter, including addressable registers and control/status information.
21.2.2 I2S Transmitter Channel Overview
Details the I2S transmitter features like word length support, clock polarity, and DMA access.
Chapter 22: AC’97 Controller
22.1 Introduction
Introduces the AC’97 Controller, its serial interface to audio codecs, and features like PCM stream and FIFO buffers.
22.1.1 Features
Lists AC’97 features: serial-to-parallel conversion, parallel-to-serial conversion, and support for sampling rates.
22.2 Interrupts
Explains that AC’97 Controller generates maskable interrupts for channels, ORed into AC97INTR.
22.2.1 Channel Interrupts
Describes individual interrupts for transmit/receive channels, readable via AC97RISRx/AC97ISRx and masked in AC97IEx.
Chapter 23: Synchronous Serial Port
23.1 Introduction
Introduces the Synchronous Serial Port (SSP) as a master/slave interface for serial communication with peripheral devices.
23.2 Features
Lists SSP features: master/slave operation, programmable clock, separate FIFO buffers, and programmable frame size.
23.3 SSP Functionality
Explains SSP functionality including programmable bit rate clock divider, interrupt outputs, and pin multiplexing.
23.4 SSP Pin Multiplex
Details SSP pin multiplexing for use with I2S controller instead of SSP.
Chapter 24: Pulse Width Modulator
24.1 Introduction
Introduces the Pulse Width Modulators (PWMs) and their features.
24.2 Theory of Operation
Explains PWM as an AMBA compliant peripheral operating on the APB bus.
24.2.1 PWM Programming Examples
Provides examples for PWM programming, including static and dynamic scenarios.
24.2.1.1 Example
Shows an example calculation for producing a PWM output.
Chapter 25: Analog Touch Screen Interface
25.1 Introduction
Introduces the touch screen controller, its support for various wire configurations and ADC.
25.2 Touch Screen Controller Operation
Explains the operation of the touch screen controller: scanning, sampling, averaging, and range checking.
25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation
Describes the 4-wire and 8-wire touch screen scanning process and register values.
25.2.2 Five-wire and Seven-wire Operation
Explains five-wire and seven-wire touch screen operation, highlighting differences in connection schemes.
Chapter 26: Keypad Interface
26.1 Introduction
Introduces the keypad interface features: 8x8 array, back drive, scan count limit, bounce time, and interrupts.
26.1.1 Features
Lists keypad interface features: 8x8 array, back drive, scan limit, bounce time, interrupt interval, low-power mode, and three-key reset.
26.2 Theory of Operation
Explains keypad scanning and key press decoding.
26.2.1 Apparent Key Detection
Describes apparent key detection caused by misinterpreting electrical signals when multiple keys are pressed.
Chapter 27: IDE Interface
27.1 Introduction
Introduces the IDE interface as an industry standard connection to ATA/ATAPI compliant devices.
27.2 Theory of Operation
Explains the IDE host's request line (DMAide), external interrupt (INTRQ), and internal interrupt (INTide).
27.2.1 Diagrams and State Machines
Shows IDE interface signal connections and controller elements.
27.2.2 PIO Operations
Details PIO operations handled by the Pin Interface unit, including register read/write and delays.
Chapter 28: GPIO Interface
28.1 Introduction
Introduces the General Purpose Input/Output (GPIO) as an APB slave module controlling various pins.
28.1.1 Memory Map
Details the GPIO base address and register properties.
28.1.2 Functional Description
Explains data registers, direction registers, and interrupt capability for enhanced GPIOs.
28.1.3 Reset
Describes GPIO register initialization on system reset.
Chapter 29: Security
29.1 Introduction
Defines security architecture for secure hardware initialization, supporting DRM and object code protection.
29.2 Features
Lists key security features: laser fuse, invisible firmware, unique encoding, disabled JTAG/external boot.
29.3 Contact Information
Provides contact information for Cirrus Logic regarding security features.
29.4 Registers
Contains register descriptions for the Security block.
Chapter 30: Glossary
Table 30-1. Glossary
Provides an alphabetical list of terms and their definitions.
Chapter 31: EP93XX Register List
Table 31-1. EP93xx Register List
Provides an alphabetical list of EP93XX registers and their page numbers.
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