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Renesas IDT CPS-10Q User Manual

Renesas IDT CPS-10Q User Manual

Central packet switch
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IDT
CPS-10Q
Central Packet Switch
User Manual
Revision 1.7
July 10, 2012

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  • Page 1 CPS-10Q   Central Packet Switch User Manual Revision 1.7 July 10, 2012...
  • Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or perfor- mance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT.

  • Page 3: Table Of Contents

    Contents Device Overview........................1-1 Device Description .......................1-1 Key Features........................1-2 Additional Resources ....................1-2 Block Diagram......................1-3 Application Example: The Wireless Basestation............1-4 Functional Overview ....................1-4 Functional Differences with PPS-Gen2 (80KSW00001) ..........1-4 sRIO Ports ..........................2-1 sRIO Port Definition .....................2-1 Trace Function ......................2-3 Packet Filtering ......................2-7 Software Assisted Error Recovery ................2-7 Switch Description ........................3-1 Conceptual Functionality....................3-1...
  • Page 4 IDT Table of Contents Reset and Initialization ......................9-1 Registers........................9-1 Initialization Steps ......................9-2 Initialization of RIO Ports .....................9-2 RIO System Bring Up....................9-2 Serdes Initialization......................9-2 Registers ..........................10-1 10.1 RapidIO Compliance....................10-1 10.2 Register Type Field Definitions ..................10-1 10.3 Address Map......................10-2 10.4 Rapid IO Registers.....................10-9 10.5 RapidIO Extended Feature Registers ..............10-19 10.6...
  • Page 5 Figures Figure 1.1 Block Diagram ........................1-3 Figure 1.2 Application Overview ......................1-4 Figure 2.1 Trace Matching Criteria ....................2-4 Figure 2.2 Illustration of the Trace Function within a Given Port ............2-5 Figure 3.1 CPS-10Q Switch Core Block Diagram................3-1 Figure 3.2 Input Buffer Diagram......................3-2 Figure 3.3 CPS-10Q PVC Mapping ....................3-3 Figure 3.4...
  • Page 6 Tables Table 2.1 Port Numbering........................2-1 Table 2.2 Port Configuration Examples ..................... 2-2 Table 4.1 EEPROM Register Address Map..................4-3 Table 4.2 Register Map Example ...................... 4-5 Table 4.3 EEPROM Format Example....................4-6 Table 4.4 I2C Address Pins ....................... 4-7 Table 5.1 Error Sources and Codes ....................
  • Page 7 IDT List of Tables Table 10.22 PORT_LINK_TO_CTRL_CSR 0x000120 ..............10-18 Table 10.23 PORT_GEN_CTRL_CSR 0x00013C................10-19 Table 10.24 RapidIO Extended Register Map................... 10-19 Table 10.25 PORT_0_LINK_MAINT_REQ_CSR 0x000140 ............. 10-20 Table 10.26 PORT_0_LINK_MAINT_RESP_CSR 0x000144 ............10-20 Table 10.27 PORT_0_LOCAL_ACKID_CSR 0x000148..............10-21 Table 10.28 PORT_0_ERR_STAT_CSR 0x000158 ................
  • Page 8 IDT List of Tables Table 10.77 ERR_LOG_RD 0xFD0004..................... 10-51 Table 10.78 SPECIAL_ERR Register Map..................10-52 Table 10.79 SPECIAL_ERR_0 0xFD0008 ..................10-52 Table 10.80 ERR_FLAG 0xFD0028 ....................10-53 Table 10.81 ERR_COUNTER 0xFD002C ..................10-54 Table 10.82 ERR_RESET 0xFD0030....................10-54 Table 10.83 QUAD_CTRL Control Registers ..................
  • Page 9 About This Manual Introduction This user’s reference manual includes hardware and software information for the CPS-10Q (80KSW0005). This device is a member of the Central Packet Switch (CPS) family. Finding Additional Information Information regarding the mechanical drawings, package pinouts, thermal characteristics, and electrical specifications can be found in the CPS-10Q datasheet.

  • Page 10: Revision History

    IDT About This Manual A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.  The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.   The compressed notation ABC[x...y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD. In double words, bit 63 is always the most significant bit and bit 0 is the least significant bit.

  • Page 11: Device Overview

    Chapter 1 Device Overview 1 DEVICE OVERVIEW The objective of this chapter is to provide an overview of the capabilities of the CPS-10Q (80KSW0005). 1.1 DEVICE DESCRIPTION The CPS-10Q functionality is optimized for line card and backplane switching. Its primary function is to switch data plane and control plane data packets via Serial Rapid IO (SRIO) between a set of devices that reside on the same line card.

  • Page 12: Key Features

    IDT Device Overview 1.2 KEY FEATURES Interfaces - sRIO  – Up to 40 Serial RapidIO (sRIO) v 1.3 full duplex lanes; 10 4x-ports and 16 1x-ports, or combina- tions thereof – Lane rates selectable; 3.125Gbps, 2.5Gbps, or 1.25Gbps – Short- or Long-haul reach for each Lane at all rates –...

  • Page 13: Block Diagram

    IDT Device Overview 1.4 BLOCK DIAGRAM Ln39 sRIO Q0 sRIO Q9 Ln38 Standard Enhanced 4 Ln37 Serial RapidIO Switch (1 port) (1 or 4 ports) Ln36 CPS-10Q Ln35 sRIO Q1 sRIO Q8 Ln34 Standard Standard Ln33 (1 port) (1 port) Ln32 Ln31 sRIO Q2...

  • Page 14: Application Example: The Wireless Basestation

    IDT Device Overview 1.5 APPLICATION EXAMPLE: THE WIRELESS BASESTATION Central switch based wireless processing Baseband System (REC) -RapidIO Based RF Card (RE) FPGA sRIO sRIO CPRI Receiver 80HFC1001 80HFC1001 CPRI FIC CPRI FIC 80HFC1000 80HFC1000 CPS-10Q CPS- 10Q CPRI FIC CPRI FIC CPS- RF Card (RE)
  • Page 15 IDT Device Overview 1.7.3 Bandwidth CPS-10Q provides a 100Gbps bandwidth. 1.7.4 PPSc Capability The CPS-10Q does not have PPSc 1.7.5 C Interface The CPS-10Q I C interface may work either in Master mode or Slave mode. 1.7.6 Broadcast and Broadcast Packet Filtering The CPS-10Q support broadcast and broadcast filtering.

  • Page 16: Srio Ports

    Chapter 2 sRIO Ports 2 sRIO PORTS sRIO PORT DEFINITION The CPS-10Q provides a total of 40 Serial RapidIO lanes that are configurable into combinations of 4x and 1x ports. Each lane supports both long- or short-haul serial transmission (as defined by version 1.3 of the Serial RIO specification).

  • Page 17: Table 2.2 Port Configuration Examples

    IDT sRIO Ports Table 2.1 Port Numbering Quad Quad Mode Lane 1X Mode Port # Lane 4X Mode Port # Number Standard 28/30 31-28 Standard 32/34 35-32 Enhanced The CPS-10Q supports lane to port assignments which are numbered from lane 0 to lane 39 in ordered fashion in groups of 10 Quad to port 0 through port 15.

  • Page 18: Packet Forwarding

    IDT sRIO Ports 2.1.4 Packet Forwarding 2.1.4.1 Store and Forward The CPS-10Q supports a “Store and Forward” methodology for packet forwarding. This methodology consists of a validation of each received packet to the SRIO specifications (including a successful CRC verification) before the packet is forwarded via the output port referenced by the destination ID in the packet header.

  • Page 19: Trace Criteria

    IDT sRIO Ports Each port provides a unique trace circuit such that the user may enable trace on up to 16 simultaneous ports (4 for each of the 16 ports) as defined below. 2.2.1 Trace Criteria The property of a given port matching a packet with a “Trace Criteria” refers to a successful comparison of the first 160 bits in a received packet to multiple pre-programmed values stored at that port.

  • Page 20: Figure 2.2 Illustration Of The Trace Function Within A Given Port

    IDT sRIO Ports RIO Packet Received at Port n of 16 Programmable Comparison 0 First 160 bits of packet Mask 0 Programmable Comparison 1 Mask 1 Trigger Programmable Comparison 2 Mask 2 Programmable Comparison 3 Mask 3 Figure 2.2 Illustration of the Trace Function within a Given Port From an application perspective, the support for comparison over the first 160 bits of the packet is to ensure that the trace function can cover the worst case RapidIO header (including those using extended addressing) plus the first 32 bits of the payload.
  • Page 21 IDT sRIO Ports 2.2.3.1 Default Trace Routing Mode In the default mode, the trace-enabled port accepts normal RapidIO traffic (referenced by the received packet’s destination ID field) as well as traffic which matches the trace criteria of all ports. Trace-triggered packets are treated by the trace-enabled output port in the same manner as it treats all other packets.

  • Page 22: Packet Filtering

    IDT sRIO Ports 2.2.7 Errored Packets The device does not trace packets with physical errors such as CRC errors and packets that are longer than 276 bytes. The device traces packets with logical errors (ex. invalid type) as long as they match the trace criteria.
  • Page 23 IDT sRIO Ports 2.4.2 Link Maintenance CSR Reset Command field A write to the Port n Maintenance CSR with the command field set to 0b011 (reset) the device will: 1) cease all current and pending transmissions (data and SRIO control symbols -- including multi- cast control symbols), 2) transmit 4 link request -- reset symbols in succession.

  • Page 24: Switch Description

    Chapter 3 Switch Description 3 SWITCH DESCRIPTION 3.1 CONCEPTUAL FUNCTIONALITY The CPS-10Q pseudo mesh architecture is a combination of full mesh and TDM. The architecture is intended to avoid numerous parallel data paths within the switch, as opposed to a centralized arbitration scheme.

  • Page 25: Input Buffers

    IDT Switch Description 3.3 SWITCH DESCRIPTION The CPS-10Q device consists of three parts; the input buffers, the switching core, and the output buffers. Each of the three portions of the switch will be described in further details in the following sub-sections. 3.3.1 Input Buffers There is separate buffer resources for maintenance packets and data packets.

  • Page 26: Switch Core

    IDT Switch Description 3.3.4 Switch Core The switch core acts like a three stage switch composed of TDM, Mesh and TDM. Mesh PVC connects QUAD to QUAD, TDM connect Port to Port inside the QUAD. The function of the switch core is moving data from input buffer to output buffer.

  • Page 27: Switching Scheduler And Priorities

    IDT Switch Description Standard Standard Standard Standard Port 0 Port 0 Port 0 Port 0 Quad 0 Quad 0 Quad 0 Quad 0 Standard Standard Standard Standard Port 1 Port 1 Port 1 Port 1 Quad 1 Quad 1 Quad 1 Quad 1 Standard Standard...
  • Page 28 IDT Switch Description 3.4.2 Output Buffer to Transmit Buffer and Transmit Buffer to Line 3.4.2.1 Unicast Packets If a tx port fails in an attempt to transmit a priority N packet (call it PA) due to CRC error, and there is a priority >N Packet (call it PB) available at the port’s retransmit buffer, then that higher priority packet PB must be the next one sent.

  • Page 29: Flow Control And Congestion Management

    IDT Switch Description 2) If the highest priority packet in the retransmit buffer (unicast OR multicast) has priority N, and a unicast or multicast packet of priority > N is being offered to the retransmit buffer by the switch's txbuf, then the retransmit buffer must accept the packet from the TXBUFs. Also, the following behavior is standard: ...

  • Page 30: I2C Interface

    Chapter 4 C Interface C Interface This chapter discusses the I C capabilities of the CPS-10Q. Overview The I C Interface is compliant with the I C Specification as a slave device and as a temporary master. The C port can be thought of primarily as a control plane access point for the CPS-10Q. An external device such as a host processor can use it to access the CPS-10Q’s registers.
  • Page 31 IDT I2C Interface When in this mode, the state of the external ADS signal is ignored. Once the CPS-10Q completes its configuration sequence (successfully or unsuccessfully), it reverts to Slave mode (where the ADS signal becomes active). 4.3.2 Commanded Master Mode The CPS-10Q can be commanded into temporary Master mode using a maintenance write to the I2C Master Control Register and I2C Master Status Control Register.

  • Page 32: Table 4.1 Eeprom Register Address Map

    IDT I2C Interface 9. Note, registers that are only 8 bits wide will only load 8 bits of data from the EEPROM. The data for subsequent registers will be every 8 bits. 10. The last two bytes of the register map represent the CRC for the image. For more information, see Calculation.

  • Page 33: Crc Calculation

    IDT I2C Interface Table 4.1 EEPROM Register Address Map (Continued) EEPROM Address (byte Bits EEPROM Contents Comments level addresses) n + 2 Bits 6:13 of the block address n + 3 Bits 14:21 of the block address Bits 22:23 are zero n + 4:n + 7 Bits 0:31 of the data to load into the above address, (n + 1) to (n + 3)

  • Page 34: Table 4.2 Register Map Example

    IDT I2C Interface for (bit_Pos = 0; bit_Pos < 8; bit_Pos++) { carry = crc[15]; if (bit_Pos_Mask & byte) serial_data = 1; else serial_data = 0; for (i=15; i>=0; i--) { if (i == 15) { crc[i] = carry ^ crc[i-1]; } else if (i == 2) { crc[i] = carry ^ crc[i-1];...

  • Page 35: Table 4.3 Eeprom Format Example

    IDT I2C Interface 4.3.7 EEPROM Format Example Table 4.3 EEPROM Format Example EEPROM Address Data Comment 0x0000 0xAA Version Number 0x0001 0xAA 0x0002 0x00 0x0003 0x02 Number of Blocks = 3 0x0004 0x00 Start of Block 1 - Register count = 1 0x0005 0x00 0x0006...

  • Page 36: Slave Mode

    IDT I2C Interface Table 4.3 EEPROM Format Example (Continued) EEPROM Address Data Comment 0x0017 0x08 Data for address 0xE00020 0x0018 0x09 Data for address 0xE00024 0x0019 0x00 Start of Block 3 - Register count = 1 0x001A 0x00 Address = 0x6c >> 2 = 0x1B 0x001B 0x00...

  • Page 37: Signaling In Slave Mode

    IDT I2C Interface Table 4.4 I C Address Pins (Continued) Name ID [0] I2C address bit 0 4.4.1 Signaling in Slave Mode Communication with the CPS-10Q in Slave mode on the I C bus supports the following cases: 1. Master device to CPS-10Q: a.

  • Page 38: Figure 4.3 Data Transfer

    IDT I2C Interface Figure 4.3 Data Transfer Figure 4.4 Acknowledgment Figure 4.5 Master Addressing a Slave with a 7-bit Address (Transfer Direction is Not Changed) Figure 4.6 Master Reads a Slave Immediately After the First Byte CPS-10Q User Manual 4 - 9 July 10, 2012 Revision 1.7 Integrated Device Technology, Inc.

  • Page 39: Figure 4.7 Combined Format

    IDT I2C Interface Figure 4.7 Combined Format Figure 4.8 Master Addresses a Slave-Receiver with 10-bit Address Figure 4.9 Master Addresses a Slave Transmitter with 10-bit Address Figure 4.10 Combined Format: Master Addresses a Slave with 10-bit Address 1.Then transmits data to slave and reads data from slave. CPS-10Q User Manual 4 - 10 July 10, 2012...

  • Page 40: Figure 4.11 Combined Format: Master Transmits Data To Two Slaves, Both With 10-Bit Address

    IDT I2C Interface Figure 4.11 Combined Format: Master Transmits Data to Two Slaves, Both with 10-bit Address 4.4.2 Connecting to Standard-, Fast-, and Hs-Mode Devices as a Slave The CPS-10Q supports Fast / Standard (F/S) modes of operation. As per the I C specification, in mixed speed communication the CPS-10Q supports HS and Fast-mode devices at 400 kbps, and Standard-mode devices at 100 kbps.

  • Page 41: Figure 4.12 Write Protocol With 10-Bit Slave Address (Ads Is 1)

    IDT I2C Interface R=1 | W=0 0 S A SLAVE ADDR DATA DATA DATA Device Device Memory Memory Memory Address [9:8] Address [7:0] Address [23:18] Address [17:10] Address [9:2] DATA DATA DATA DATA Input Data Input Data Input Data Input Data [31:24] [23:16] [15:8]...

  • Page 42: Figure 4.15 Read Protocol With 7-Bit Slave Address (Ads Is 0)

    IDT I2C Interface R=1 | W=0 SLAVE ADDR DATA DATA DATA Device Memory Memory Memory Address [6:0] Address [23:18] Address [17:10] Address [9:2] R=1 | W=0 SLAVE ADDR DATA DATA DATA DATA Device Output Data Output Data Output Data Output Data Address [6:0] [31:24] [23:16]...

  • Page 43: Error Management

    Chapter 5 Error Management 5 ERROR MANAGEMENT The CPS-10Q provides the ability to record, manage, and report, errors and status information. The logic required to support this functionality is collectively known as “Error Management.” 5.1 ERROR MANAGEMENT FUNCTIONAL ARCHITECTURE The device’s error management functionality consists of a number of data structures as shown in the diagram below.
  • Page 44 IDT Error Management Table 5.1 Error Sources and Codes Error Source Code Quad 4 (Lane 2) 0x3C Quad 4 (Lane 3) 0x3B Quad 5 0x3A Quad 6 0x39 Quad 7 0x3D Quad 8 0x3E Quad 9 (Lane 0) 0x1C Quad 9 (Lane 1) 0x1D Quad 9 (Lane 2) 0x27...

  • Page 45: Table 5.3 Jtag Errors And Codes -- Group Number 0X2

    IDT Error Management Table 5.2 I C Errors and Codes -- Group Number 0x1 Error Code Description Ack Error 0x11 This error references an event when an acknowl- edgement is expected but is not received. This error can occur in Master or slave mode. If the error happens in Master mode, the data transfer will be terminated and the error will be captured.

  • Page 46: Table 5.4 Maintenance Handler Errors And Codes -- Group Number 0X3

    IDT Error Management 5.1.1.3 Maintenance Handler Errors The Maintenance Handler errors shown in the table below are detectable by the device. If Maintenance Handler error reporting is enabled each of the errors defined below is sent to the Error Log when detected. Table 5.4 Maintenance Handler Errors and Codes -- Group Number 0x3 Error Code...

  • Page 47: Table 5.5 Configuration Errors And Codes -- Group Number 0X5

    IDT Error Management 5.1.1.4 Configuration Errors The device supports the ability to detect the following configuration errors. If configuration error reporting is enabled each of the errors defined below is sent to the Error Log when detected. Table 5.5 Configuration Errors and Codes -- Group Number 0x5 Error Code Description...

  • Page 48: Table 5.6 Rio Serdes Errors And Codes -- Group Number 0X6

    IDT Error Management 5.1.1.5 RIO SERDES Errors The device supports the ability to detect the following RIO SERDES errors. If SERDES quad error reporting is enabled each of the errors defined below is sent to the Error Log when detected. Table 5.6 RIO SERDES Errors and Codes -- Group Number 0x6 Error Code...

  • Page 49: Table 5.8 Rio Link Protocol Errors And Codes - Group Number 0X8

    IDT Error Management 5.1.1.7 RIO Link Protocol Errors The device supports the ability to detect the following RIO Link Protocol errors. If Port level error reporting is enabled each of the errors defined below is sent to the Error Log when detected. Table 5.8 RIO Link Protocol Errors and Codes –...

  • Page 50: Table 5.9 Rio Logical And Transport Errors And Codes -- Group Number 0X9

    IDT Error Management Table 5.8 RIO Link Protocol Errors and Codes – Group Number 0x8 Error Code Description Fatal link response 0x8C Triggered when 16 link timeouts occur while waiting for a link timeout encountered response. Reported only when Port error reporting is enabled. Link Timeout 0x8D Triggered when a link timeout is encountered.
  • Page 51 IDT Error Management Error Code Description Dropped packet -- 0x99 Triggered when a packet in the retransmit buffer has been CRC retransmit limit retransmitted the configured maximum number of times due to the reception of a packet_not_accept control symbol with bad CRC status.
  • Page 52 IDT Error Management 5.1.2.4 Error Counter The device provides an Error Counter. The user is capable, through use of the Special Error Filter Register, to define which of 8 specific errors, when detected, will increment this counter. The Error Counter is a 16- bit counter.

  • Page 53: Table 5.10 Port Write Payload Definition

    IDT Error Management Table 5.10 Port Write Payload Definition Error Error Error Error Reserved Reserved Source Code Flags Counter 6 bit 8 bits 8 bits 16 bits 00000000000000000000000 The full maintenance packet generated appear as shown in the following table with the values described below Table 5.11 Maintenance Packet Format AckID...

  • Page 54: Jtag & Boundary Scan

    Chapter 6 JTAG & Boundary Scan 6 JTAG & BOUNDARY SCAN The CPS-10Q supports all the mandatory instructions defined in the IEEE 1149.1 specification. To support production testing, the device supports private instructions for Memory BIST and Scan Testing. The TAP controller allows access to the configuration registers.

  • Page 55: Device Id Register

    IDT JTAG & Boundary Scan Table 6.1 Test Instructions IR Code [3:0] Instruction Comments Die_Signature Dumps fab information including die location, version, and wafer number Bypass Implemented per IEEE 1149.1-2001 6.3 DEVICE ID REGISTER The JTAG Device ID register length is 32 bits wide. The Capture Data Register value is the Device ID. The JTAG Device ID register is mapped to the DEV_IDENT field in the DEV_IDENT_CAR as defined in the “Registers”...

  • Page 56: Boundary Scan

    IDT JTAG & Boundary Scan 6.5.1 Configuration Register Access -- Writes When bit 0 of the data stream is 0, data shifted in after the address is written to the address specified in jtag_config_addr. The TDO pin will transmit all 0s. Timing is shown below. Exit1_dr Exit2_dr Exit1_dr...

  • Page 57: Reference Clock

    Chapter 7 Reference Clock 7 REFERENCE CLOCK The CPS-10Q uses a reference clock (REF_CLK) to generate its RIO PHY and internal clocks. This section outlines the definition of this clock and the auxiliary clocks used for testing. 7.1 REFERENCE CLOCK SPECIFICATION The CPS-10Q internal timing is based on a AC coupled Reference Clock as specified below.

  • Page 58: Programming The Device

    Chapter 8 Programming the Device 8 PROGRAMMING THE DEVICE This chapter focuses on actual real-world usage of the device. This covers configuring and using the switch. 8.1 DEVICE ACCESS The device can be programmed through three different interfaces: in-band through any of the RIO ports, or out of band through the I C &...

  • Page 59: Table 8.2 Rio Defined Maintenance Response Packet Generated By Cps-10Q

    IDT Programming the Device As the response to a Maintenance Request Packet, a Maintenance Response Packet is created using the format below with the hop_count field set to 0xFF. Responses are sent via the port on which the Mainte- nance Packet was received. Table 8.2 RIO Defined Maintenance Response Packet generated by CPS-10Q AckID rsvd...

  • Page 60: Route Tables

    IDT Programming the Device 8.1.3 JTAG access Please refer to JTAG chapter. 8.2 ROUTE TABLES 8.2.1 Route Tables The CPS-10Q provides route tables which are used to determine the port(s) to which packets must be output. The CPS-10Q performs lookups into these route tables to associate the destination ID of each received packet with an output port configuration.

  • Page 61: Figure 8.1 Route Table Lookup Diagram

    IDT Programming the Device destination ID [15:8] Enable Destination Domain No Match Comparison Domain Domain Route Table Lookup Comparison 16 bit Comparison Matches destination ID [15:8] = 0x00 field Device ID Size Packet Packet Force References Select Enable Local? Device Domain Destination 8 bit Device...

  • Page 62: Table 8.3 Cps-10Q Default Port Configuration

    IDT Programming the Device Destination ID associations in the route tables are dependent upon the port configurations of the device. The CPS-10Q supports the ability for the user to modify the QUAD_CTRL registers and the PORT_CTRL_CSRs to configure the device’s ports. Specifically, these register definitions determine the number of ports that are available at any time.
  • Page 63 IDT Programming the Device Block writes (i.e. writing four consecutive entries into the route table) are also supported. In the case of a block write, if the 8 MSBs of a 16-bit destination ID do not match the value programmed in the RIO_Domain register, only one entry is written into the Domain Route Table.

  • Page 64: Table 8.4 Multicast Mask Register References For Multicast Mask Port Csr Usage

    IDT Programming the Device 3) the Block Association Model Part 9 of the RIO Specification states that only non-response transactions are allowed to use multicast. Further, Priority 3 packets should not be used since it's reserved for responses. Unexpected behavior can results in the event of priority 3 multicast transactions are used. 8.2.7 Multicast Mask Register The CPS-10Q device provides 40 Multicast Mask Registers for each port.

  • Page 65: Table 8.5 Region Select

    IDT Programming the Device Table 8.4 Multicast Mask Register References for Multicast Mask Port CSR Usage Mask Register 8.2.9 Destination Address to Route Table Mapping CPS-10Q use Destination Addresses in the route tables in order to determine the proper output mapping of a given packet.

  • Page 66: Table 8.7 Multicast Mask References

    IDT Programming the Device Table 8.6 Port Number References Port Number Port number references are supported in both the Domain Route Table and the Device Route table. 8.2.9.2 Multicast Mask References The device supports the ability to multicast packets to multiple output ports. In support of this, the Multicast Mask Registers must be referenced in the Device Route Table.

  • Page 67: Device Programming

    IDT Programming the Device 8.2.9.4 No Route The CPS-10Q supports references to “no route” in both its Device Route Table and its Domain Route Table. To reference “no route” the user uses a value of 0xDF. If this value is encountered as a result of a lookup into either of its route tables, the device will drop the packet.

  • Page 68: Per Port Reset

    IDT Programming the Device 8.3.2 Per Port Reset Per Port reset is reset to a single port only which is invoked when that port receives a sequence of four link- request or reset-device controls (also called a link-reset) as described by the sRIO spec in part-6. The reception of a local reset to the port in this way is referred to below as a local soft reset event and affects the port in the following way: 1.

  • Page 69: Reset Configuration

    IDT Programming the Device 16. There is an ackid scoreboard in the output side of the port which tracks the ackids that are in use (ie- outstanding on transmitted but unacknowledged packets). It also tracks the value of ackid to be transmitted in the next outbound packet as well as tracks the value of the ackid expected in the next acknowledge control symbol (accept, retry, or link-response) which the port receives.
  • Page 70 IDT Programming the Device 8.3.5 Error Report Enables To detect errors as early as possible (even those during the initial programming sequence), the error reporting features of the CPS-10Q is taken advantage of in this early stage of configuring the CPS-10Q. Errors are reported from any of several major architectural blocks aboard the CPS-10Q.

  • Page 71: Example Of Programming

    IDT Programming the Device 8.4 EXAMPLE OF PROGRAMMING There are only three steps to program the CPS-10Q switch route. 1. Program the QUAD_CTRL_Register (0xFF0000 - 0xFF9000). Quad Mode (bit 5): Standard or Enhance Quad Speed (bit 1-0): 3.125, 2.5 or 1.25 Gbps. Transmitter Pre- emphasis (bit 4-2), Drive Strength (bit 9-7) 2.

  • Page 72: July 10, 2012

    IDT Programming the Device MC_Read  – This function reads the contents of a multicast (MC) list, identifying which ports are active. MC_Delete  – This function deletes user-specified individual member ports of a multicast (MC) list. CPS-10Q User Manual 8 - 15 July 10, 2012 Revision 1.7...

  • Page 73: Reset And Initialization

    Chapter 9 Reset and Initialization 9 RESET AND INITIALIZATION 9.1 REGISTERS The registers for the CPS-10Q supports the “Reset Values” defined in the “Registers” section of this docu- ment. 9.1.1 RIO Ports After Power Up and after device reset, the RIO Port configuration is as defined below: Table 9.1 Port Configuration at Power Up Lane Port Mode...

  • Page 74: Initialization Steps

    IDT Reset and Initialization The device provides two external pins, (SPD0 and SPD1) which determines the initial (default) port speed. These pins support the configurations defined below: Table 9.2 Default Speed Settings with SPD0 and SPD1 SPD0/SPD1 States Port Speed 1.25 Gbits/sec 2.5 Gbits/sec 3.125 Gigabits/sec...

  • Page 75: Registers

    Chapter 10 Registers 10REGISTERS The register file addressable through I C, JTAG and any RapidIO port and is built with 22-bit addresses and 32-bit words, as specified by the RIO spec. All unused address space is to be considered RESERVED. When write to any RESERVED address, no error is reported, and nothing happens.

  • Page 76: Address Map

    IDT Registers Table 10.1 Register Types Type Description Fixed Read. The values in these registers are fixed and can be only read from an external device. Write Once Reset. 10.3 ADDRESS MAP A mapping of registers to addresses exists as part of the overall memory address map of the device. This memory map is provided below.
  • Page 77 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0x000100 - 0x0002BC RIO Extended Feature Registers 0x000100 PORT_MAINT_BLK_HEAD 0x000120 PORT_LINK_TIME_OUT_CTRL_CSR 0x00013C PORT_GEN_CTRL_CSR 0x000140 PORT_0_LINK_MAINT_REQ_CSR 0x000144 PORT_0_LINK_MAINT_RESP_CSR 0x000148 PORT_0_LOCAL_ACKID_CSR 0x000158 PORT_0_ERR_N_STAT_CSR 0x00015C PORT_0_CTRL_CSR 0x000140+ Registers start for port PORT_NUM 0x20*PORT_NUM 0x000320 PORT_15_LINK_MAINT_REQ_CSR 0x000324...
  • Page 78 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0xE40000 Port 0 Trace Comparison Value 1 0xE40014 Port 0 Trace Mask 1 0xE40028 Port 0 Trace Comparison Value 2 0xE4003C Port 0 Trace Mask 2 0xE40050 Port 0 Trace Comparison Value 3 0xE40064 Port 0 Trace Mask 3 0xE40078...
  • Page 79 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0xF20000 - F20100 Global Configuration Registers 0xF20000 - 0xF20008 Reserved 0xF2000C CPS_CONTROL 0xF20010 Vendor access only 0xF20014 CONF_MOD_ERR_REPORT_ENABLE 0xF20018 AUXPORT_ERR_REPORT_ENABLE 0xF2001C MAINT_ERR_REPORT_ENABLE 0xF20020 RIO_DOMAIN 0xF20024 RIO_PORT_WRITE_INFO 0xF20028 RIO_PORT_WTE_SRCID 0xF2002C RIO_ASSY_IDENT_CAR 0xF20030 RIO_ASSY_INF_CAR 0xF20034...
  • Page 80 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0xF38900 - 0xF3899C Port 9 Unique Multicast Masks 0xF38A00 - 0xF38A9C Port 10 Unique Multicast Masks 0xF38B00 - 0xF38B9C Port 11 Unique Multicast Masks 0xF38C00 - 0xF38C9C Port 12 Unique Multicast Masks 0xF38D00 - 0xF38D9C Port 13 Unique Multicast Masks 0xF38E00 - 0xF38E9C...
  • Page 81 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0xF40F0C PORT_15_SWITCH_BUF_STATUS 0xF40F10 PORT_15_ACK_CNTR 0xF40F14 PORT_15_NACK_CNTR 0xF40F18 Reserved 0xF40F1C PORT_15_SW_PKT_CNTR 0xF40F20 PORT_15_TRACE_MATCH_CNTR_1 0xF40F24 PORT_15_TRACE_MATCH_CNTR_2 0xF40F28 PORT_15_TRACE_MATCH_CNTR_3 0xF40F2C PORT_15_TRACE_MATCH_CNTR_4 0xF40F30 PORT_15_FILTER_MATCH_CNTR_1 0xF40F34 PORT_15_FILTER_MATCH_CNTR_2 0xF40F38 PORT_15_FILTER_MATCH_CNTR_3 0xF40F3C PORT_15_FILTER_MATCH_CNTR_4 0xF4FF00 - 0xF4FF08 Broadcast to Switchport Registers 0xF4FF00 PORT_BUF_SIZE_BROADCAST 0xF4FF04...
  • Page 82 IDT Registers Table 10.2 CPS-10Q Memory Map Base Address Description 0xFD002C ERR_COUNTER 0xFD0030 ERR_RESET 0xFF0000 - 0xFFF000 Quad Control Registers 0xFF0000 QUAD_0_CTRL 0xFF0004 QUAD_0_ERR_REPORT_EN 0xFF1000 QUAD_1_CTRL 0xFF1004 QUAD_1_ERR_REPORT_EN 0xFF9000 QUAD_9_CTRL 0xFF9004 QUAD_9_ERR_REPORT_EN 0xFFF000 QUAD_CTRL_BROADCAST CPS-10Q User Manual 10 - 8 July 10, 2012 Revision 1.7 Integrated Device Technology, Inc.

  • Page 83: Rapid Io Registers

    IDT Registers 10.4 RAPID IO REGISTERS Rapid IO specifications rev 1.3 specifies that certain registers be provided. These required registers is implemented as defined in this section. 10.4.1 Device Identity Capability Register (DEV_IDENT_CAR) Table 10.3 DEV_IDENT_CAR 0x000000 Reset Field Name Type Comment Value...

  • Page 84: Table 10.7 Proc_Elem_Feat_Car 0X000010

    IDT Registers 10.4.4 Assembly Information Capability Register (ASSY_INF_CAR) Table 10.6 ASSY_INF_CAR 0x00000C Reset Field Name Type Comment Value 15 - 0 EXT_FEAT_PTR 0x0100 Pointer to the first entry in the extended features list. 31 - 16 ASSY_REV 0x0000 Assembly revision level. The reader is referred to the RIO_ASSY_INF_CAR 10.4.5 Processing Element features Capability Register...

  • Page 85: Table 10.8 Switch_Port_Inf_Car 0X000014

    IDT Registers Table 10.7 PROC_ELEM_FEAT_CAR 0x000010 Reset Field Name Type Comment Value STANDARD_ROUTE_CONFIGUR The device supports the standard ATION_SUPPORT route table configuration mecha- nism 1 = supported EXTENDED_ROUTE_CONFIGUR The device supports extended ATIO_SUPPORT route table configuration 1 = supported MULTICAST_SUPPORT The device supports multicast extensions 1 = supported...

  • Page 86: Table 10.9 Src_Ops_Car 0X000018

    IDT Registers Table 10.8 SWITCH_PORT_INF_CAR 0x000014 Reset Field Name Type Comment Value 31 - 16 Reserved 10.4.7 Source Operations Capabilities Register (SRC_OPS_CAR) Table 10.9 SRC_OPS_CAR 0x000018 Reset Field Name Type Comment Value 1 - 0 Reserved PORT_WRITE Defines the ability of the device to source a port write operation 0 = no 1 = yes...

  • Page 87: Table 10.10 Sw_Mcast_Sup_Car 0X000030

    IDT Registers Table 10.9 SRC_OPS_CAR 0x000018 Reset Field Name Type Comment Value DOORBELL Defines the ability of the device to support a doorbell operation 0 = no 1 = yes DATA_MESSAGE Defines the ability of the device to support a data message operation 0 = no 1 = yes WRITE_WITH_RESPONSE...

  • Page 88: Table 10.11 Sw_Rte_Tbl_Lim_Car 0X000034

    IDT Registers 10.4.9 Switch Route Table Entries Table Limit Capabilities Register (SW_RTE_TBL_LIM_CAR) Table 10.11 SW_RTE_TBL_LIM_CAR 0x000034 Reset Field Name Type Comment Value 15 - 0 MAXIMUM_DESTINATION 0xFF Maximum number of configurable des- _IDS_SUPPORTED tination IDs that are supported (0xFF = 256) 31 - 16 Reserved...

  • Page 89: Table 10.15 Std_Rte_Conf_Destid_Sel_Csr 0X000070

    IDT Registers 10.4.12 Component Tag Command and Status Register (COMPONENT_TAG_CSR) Table 10.14 COMPONENT_TAG_CSR 0x00006C Reset Field Name Type Comment Value 31 - 0 COMPONENT_TAG 0x00 Component Tag for this device 10.4.13 Standard Route Table Entries Configuration Destination ID Select Com- mand and Status Register (STD_RTE_CONF_DESTID_SEL_CSR) The use of bits [19:16] are not sRIO compliant.

  • Page 90: Table 10.17 Std_Rte_Default_Port 0X000078

    IDT Registers Table 10.16 STD_RTE_CONF_PORT_SEL_CSR 0x000074 Reset Field Name Type Comment Value 23 - 16 CONF_OUT_PORT_2 0x00 Destination value through which all mes- sages intended for CON_DESTID + 2 are sent. 31 - 24 CONF_OUT_PORT_3 0x00 Destination value through which all mes- sages intended for CON_DESTID + 3 are sent.

  • Page 91: Table 10.18 Mcast_Mask_Port 0X000080

    IDT Registers 10.4.16 Multicast Mask Port Command and Status Register (MCAST_MASK_PORT) Table 10.18 MCAST_MASK_PORT 0x000080 Reset Field Name Type Comment Value PORT_PRESENT Indication of the existence of the egress port and multicast mask pair as a result of the last Write_to_Verify command.

  • Page 92: Table 10.20 Mcast_Assoc_Op_Csr 0X000088

    IDT Registers 10.4.18 Multicast Association Operations Command and Status Register (MCAST_ASSOC_OP_CSR) Table 10.20 MCAST_ASSOC_OP_CSR 0x000088 Reset Field Name Type Comment Value ASSOCIATION_PRESENT Contains the result of the last write to ver- ify command. 0 = no association 1 = association present 4 - 1 Reserved 6 - 5...

  • Page 93: Rapidio Extended Feature Registers

    IDT Registers 10.4.21 Port General Control Command and Status Register (PORT_GEN_CTRL_CSR) Table 10.23 PORT_GEN_CTRL_CSR 0x00013C Reset Field Name Type Comment Value 28 - 0 Reserved DISCOVERED 0 = device not discovered 1 = device discovered 31 - 30 Reserved 10.5 RAPIDIO EXTENDED FEATURE REGISTERS Table 10.24 RapidIO Extended Register Map Base Address (hex) Associated Registers...

  • Page 94: Table 10.25 Port_0_Link_Maint_Req_Csr 0X000140

    IDT Registers 10.5.1 Port 0 Link Maintenance Request Command and Status Register (PORT_0_LINK_MAINT_REQ_CSR) Table 10.25 PORT_0_LINK_MAINT_REQ_CSR 0x000140 Reset Field Name Type Comment Value 2 - 0 Command 0b000 0b011 = Reset device 0b100 = Input status 0b000 - 0b010 = Reserved 0b101 - 0b111 = Reserved See RIO part 6 table 3-6 (rev 1.3) 31 - 3...

  • Page 95: Table 10.27 Port_0_Local_Ackid_Csr 0X000148

    IDT Registers 10.5.3 Port 0 Local ACKID Command and Status Register (PORT_0_LOCAL_ACKID_CSR) Table 10.27 PORT_0_LOCAL_ACKID_CSR 0x000148 Reset Field Name Type Comment Value 4 - 0 OUTBOUND_ACKID 0b00000 The next transmitted ackID value for the port. Writing this value can force retransmission of outstanding unac- knowledged packets in order to manually implement error recovery...
  • Page 96 IDT Registers Table 10.28 PORT_0_ERR_STAT_CSR 0x000158 Reset Field Name Type Comment Value Reserved PORT_WRITE_PENDING Pending Port Write 7 - 5 Reserved INPUT_ERROR Input Error - Port is stopped INPUT_ERROR_ENCOUNTERED Input Error was encountered INPUT_RETRY Input Retry - Port is stopped 15 - 11 Reserved OUTPUT_ERROR...
  • Page 97 IDT Registers Table 10.29 PORT_0_CTRL_CSR 0x00015C Reset Field Name Type Comment Value PORT_DISABLE Port Disable 26 - 24 PORT_WIDTH_OVERRIDE 0b000 000 = no override 010 = single lane port lane 0 011 = single lane port lane 2 Others reserved 29 - 27 INIT_PORT_WIDTH 0b000...

  • Page 98: Idt Specific Rapidio Extended Feature Registers

    IDT Registers 10.6 IDT SPECIFIC RAPIDIO EXTENDED FEATURE REGISTERS 10.6.1 Local Route Configuration Destination ID Select Command and Status Register (LOCAL_RTE_CONF_DESTID_SEL_CSR) Table 10.30 LOCAL_RTE_CONF_DESTID_SEL_CSR 0x010070 Reset Field Name Type Comment Value 4 - 0 PORT_ROUTE_TABLE 0b00000 Defines the port whose route table is affected _SELECTION when a write to or a read from the Standard Route Configuration Port Select CSR is...

  • Page 99: Table 10.31 Local_Mcast_Mask_Port_Sel 0X010080

    IDT Registers 10.6.2 Local Multicast Mask Port Select Table 10.31 LOCAL_MCAST_MASK_PORT_SEL 0x010080 Reset Field Name Type Comment Value 4 - 0 PORT_MCAST_SELE 0b00000 Defines the port whose mcast masks are CTION affected when a write to or a read from the Standard Mcast mask Port CSR (0x00080) is made.

  • Page 100: Routing Table Registers

    IDT Registers 10.7 ROUTING TABLE REGISTERS Table 10.32 Routing Table Register Base Addresses (Hex) Associated Registers 0xE00000 Global Device Route Table for Device ID 0x00 0xE00004 Global Device Route Table for Device ID 0x01 0xE003FC Global Device Route Table for Device ID 0xFF 0xE00400 Global Domain Route Table for Device ID 0x00 0xE00404...

  • Page 101: Trace Registers

    IDT Registers Table 10.33 Route Table Register 0xE00000-0xE1F7FC Field Name Type Reset Value Comment Port_Number 0xDE 0x00 - x0F for unicast port number 0-15. 0x40 - x67 for multicast register 0 - 39 10.8 TRACE REGISTERS Table 10.34 Trace Register Map Base Addresses (Hex) Associated Registers 0xE40000-0xE40024...

  • Page 102: Table 10.35 Port_0_Trace_Value_1_Block_0 0Xe40000

    IDT Registers 10.8.1 Port 0 Trace Comparison Value 1 Registers Table 10.35 Port_0_Trace_Value_1_Block_0 0xE40000 Field Name Type Reset Value Comment 31 - 0 COMPARISON_VALUE_1_BLOCK_0 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet.

  • Page 103: Table 10.37 Port_0_Trace_Value_1_Block_2 0Xe40008

    IDT Registers Table 10.37 Port_0_Trace_Value_1_Block_2 0xE40008 Reset Field Name Type Comment Value 31 - 0 COMPARISON_VALUE 0x00000000 This value will be used for a bit by bit _1_BLOCK_2 comparison against the first 32 bits received in the packet. Bit 31 will be compared to the 65th packet bit Bit 30 will be compared to the 66th packet bit...

  • Page 104: Table 10.39 Port_0_Trace_Value_1_Block_4 0Xe40010

    IDT Registers Table 10.39 Port_0_Trace_Value_1_Block_4 0xE40010 Reset Field Name Type Comment Value 31 - 0 COMPARISON_VALUE_1_BLOCK_4 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet. Bit 31 will be compared to the 129th packet bit Bit 30 will be compared to the 130th packet bit...

  • Page 105: Table 10.41 Port_0_Mask_Value_1_Block_1 0Xe40018

    IDT Registers Table 10.41 Port_0_MASK_Value_1_Block_1 0xE40018 Reset Field Name Type Comment Value 31 - 0 MASK_VALUE_1_BLOCK_1 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet. Bit 31 will be a mask for the 33rd pack comparison bit Bit 30 will be a mask for the 34th comparison bit...

  • Page 106: Table 10.43 Port_0_Mask_Value_1_Block_3 0Xe40020

    IDT Registers Table 10.43 Port_0_Mask_Value_1_Block_3 0xE40020 Field Name Type Reset Value Comment 31 - 0 MASK_VALUE_1_BLOCK_3 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet. Bit 31 will be a mask for the 97th comparison bit Bit 30 will be a mask for the 98th comparison bit...

  • Page 107: Global Configuration Registers

    IDT Registers 10.9 GLOBAL CONFIGURATION REGISTERS 10.9.1 Control Register (CPS_CONTROL) Table 10.45 CPS_CONTROL 0xF2000C Reset Field Name Type Comment Value PORT_RESET_BEHAVIOR Defines action upon reception of an sRIO reset control symbol (0 = reset chip, 1 = reset port via which the symbol was received) 4 - 1 TRACE_OUTPUT_PORT_E...

  • Page 108: Table 10.46 Conf_Mod_Err_Report_Enable 0Xf20014

    IDT Registers Table 10.45 CPS_CONTROL 0xF2000C Reset Field Name Type Comment Value QUAD_OFF_3 0: On; 1: Off Quad 5 and Quad 6; sleep mode for power reduction QUAD_OFF_4 0: On; 1: Off Quad 7 and Quad 8; sleep mode for power reduction QUAD_OFF_5 0: On;...

  • Page 109: Table 10.47 Auxport_Err_Report_Enable 0Xf20018

    IDT Registers 10.9.3 Auxiliary Port Error Report Enable Register (AUXPORT_ERR_REPORT_ENABLE) This register is used to enable/disable error reporting to the Error Manager from the device’s JTAG and/or C logic. Table 10.47 AUXPORT_ERR_REPORT_ENABLE 0xF20018 Reset Field Name Type Comment Value JTAG_ERR_REPORT_ENABLE 0 = Disable JTAG Error Reporting 1 = Enable JTAG Error Reporting C_ERR_REPORT_ENABLE...

  • Page 110: Table 10.50 Rio_Port_Write_Info 0Xf20024

    IDT Registers 10.9.6 Rapid IO Port Write Information (RIO_PORT_WRITE_INFO) This register will used to define the priority and the destination_ID that the device will use for Port-Write Packets. Table 10.50 RIO_PORT_WRITE_INFO 0xF20024 Reset Field Name Type Comment Value 12 - 0 Reserved 14 - 13 PRIO...

  • Page 111: Table 10.53 Rio_Assy_Inf_Car 0Xf20030

    IDT Registers 10.9.8 Rapid IO Assembly Identification Capability Register (RIO_ASSY_IDENT_CAR) This register is used to provide the user control over the values that are used in the RIO defined ASSY_IDENT_CAR. Table 10.52 RIO_ASSY_IDENT_CAR 0xF2002C Reset Field Name Type Comment Value 15 - 0 RIO_ASSY_VENDOR_IDENT 0x0000...

  • Page 112: Table 10.55 I2C_Master_Ctrl 0Xf20050

    IDT Registers 10.9.11 I2C Master Control (I2C_MASTER_CTRL) Table 10.55 I2C_MASTER_CTRL 0xF20050 Field Name Type Reset Value Comment 9 - 0 EPROM_SLAVE_ADDR 0b0001010[ID2][ID1][ID0] I2C address to use for the EPROM for commanded master mode Reserved CHKSUM_DISABLE 0 = Verify checksum with EPROM read 1 = Do not verify checksum with EPROM read...

  • Page 113: Table 10.56 I2C_Master_Stat_Ctrl 0Xf20054

    IDT Registers 10.9.12 I2C Master Status Control (I2C_MASTER_STAT_CTRL) Table 10.56 I2C_MASTER_STAT_CTRL 0xF20054 Reset Field Name Type Comment Value 15 - 0 EPROM_START_ADDR 0x0000 EPROM address offset where I2C Master read operation take place START_I2C_EPROM_READ Setting this bit to logical one will initiate the start of an I2C EPROM read 19 - 17...
  • Page 114 IDT Registers Table 10.56 I2C_MASTER_STAT_CTRL 0xF20054 Reset Field Name Type Comment Value I2C_NACK A value of 1 indicates that an expected ack was not received Reset on read I2C_UNEXP_START_STOP A value of 1 indicates that an unexpected I2C start or stop was detected Reset on read I2C_BAD_IMG_VERSION...

  • Page 115: Multicast Registers

    IDT Registers 10.10 MULTICAST REGISTERS Table 10.57 MULTICAST Register Map Base Address (Hex) Associated Registers 0xF30000 Global MULTICAST0 0xF30004 Global MULTICAST1 0xF3009C Global MULTICAST39 0xF38000 Port 0 MULTICAST0 0xF38004 Port 0 MULTICAST1 0xF3809C Port 0 MULTICAST39 0xF38100 Port 1 MULTICAST0 0xF38104 Port 1 MULTICAST1 0xF3819C...

  • Page 116: Table 10.58 Multicast Mask Register (0Xf30000-0Xf38F9C)

    IDT Registers 10.10.1 Multicast Mask 0 (MULTICAST0) Table 10.58 Multicast Mask Register (0xF30000–0xF38F9C) Reset Field Name Type Comment Value MCAST_PORT_0 0 = Port 0 is not included in Multicast group 0 1 = Port 0 is included in Multicast group 0 MCAST_PORT_1 0 = Port 1 is not included in Multicast group 0 1 = Port 1 is included in Multicast group 0...

  • Page 117: Switching Port Registers

    IDT Registers 10.11 SWITCHING PORT REGISTERS Table 10.59 Switching Port Register Map Base Address (hex) Associated Registers 0xF40000-0xF4003C Switching Port 0 Registers 0xF40100-0xF4013C Switching Port 1 Registers 0xF40200-0xF4023C Switching Port 2 Registers 0xF40300-0xF4033C Switching Port 3 Registers 0xF40400-0xF4043C Switching Port 4 Registers 0xF40500-0xF4053C Switching Port 5 Registers 0xF40600-0xF4063C...

  • Page 118: Table 10.61 Port_0_Ops 0Xf40004

    IDT Registers Table 10.60 PORT_0_BUF_SIZE 0xF40000 Reset Field Name Type Comment Value 23 - 20 Reserved 27 - 24 PRI_3_BUF_SIZE 0b0010 RIO Priority Level 3 Input Buffer Size 31 - 25 Reserved 10.11.2 Port 0 Operations (PORT_0_OPS) Table 10.61 PORT_0_OPS 0xF40004 Reset Field Name Type...
  • Page 119 IDT Registers Table 10.61 PORT_0_OPS 0xF40004 Reset Field Name Type Comment Value ENABLE_TRACE_COMPARISON_1 0 = Trace Comparison Value 1 is disabled 1 = Trace Comparison Value 1 is enabled ENABLE_TRACE_COMPARISON_2 0 = Trace Comparison Value 2 is disabled 1 = Trace Comparison Value 2 is enabled ENABLE_TRACE_COMPARISON_3 0 = Trace Comparison Value 3...

  • Page 120: Table 10.62 Port_0_Err_Report_Enable 0Xf40008

    IDT Registers 10.11.3 Port 0 Error Report Enable (PORT_0_ERR_REPORT_ENABLE) Table 10.62 PORT_0_ERR_REPORT_ENABLE 0xF40008 Reset Field Name Type Comment Value ERROR_REPORT_ENABLE 0 = Disable Error Reporting from this port 1 = Enable Error Reporting from this port SWITCH_PORT_ERROR_REPORT_ 0 = Disable error reporting from ENABLE switch buffers 1 = Enable error reporting from...

  • Page 121: Table 10.64 Port_0_Ack_Cntr 0Xf40010

    IDT Registers Table 10.63 PORT_0_SWITCH_BUF_STATUS 0xF4000C Reset Field Name Type Comment Value PRI_0_OUTPUT_BUF_ALMOST_FULL_STATUS 0 = Not Almost Full 1 = Almost Full PRI_1_OUTPUT_BUF_ALMOST_FULL_STATUS 0 = Not Almost Full 1 = Almost Full PRI_2_OUTPUT_BUF_ALMOST_FULL_STATUS 0 = Not Almost Full 1 = Almost Full PRI_3_OUTPUT_BUF_ALMOST_FULL_STATUS 0 = Not Almost Full 1 = Almost Full...

  • Page 122: Table 10.67 Port_0_Trace_Match_Cntr_1 0Xf40020

    IDT Registers 10.11.8 Port 0 Trace Match Counter Value 1 (PORT_0_TRACE_MATCH_CNTR_1) Table 10.67 PORT_0_TRACE_MATCH_CNTR_1 0xF40020 Field Name Type Reset Value Comment 31 - 0 TRACE_COUNT_1 0x00000000 A saturating count of packets at port 0 that have met the defined trace criteria with comparison Value 1 10.11.9 Port 0 Trace Match Counter Value 2 (PORT_0_TRACE_MATCH_CNTR_2) Table 10.68 PORT_0_TRACE_MATCH_CNTR_2 0xF40024...

  • Page 123: Table 10.71 Port_0_Filter_Match_Cntr_1 0Xf40030

    IDT Registers 10.11.12 Port 0 Filter Match Counter Value 1 (PORT_0_FILTER_MATCH_CNTR_1) Table 10.71 PORT_0_FILTER_MATCH_CNTR_1 0xF40030 Field Name Type Reset Value Comment 31 - 0 FILTER_COUNT_1 0x00000000 A saturating count of packets that have met the defined filter criteria with compari- son Value 1 10.11.13 Port 0 Filter Match Counter Value 2 (PORT_0_FILTER_MATCH_CNTR_2) Table 10.72 PORT_0_FILTER_MATCH_CNTR_2 0xF40034...

  • Page 124: Table 10.75 Trace Register Map

    IDT Registers Table 10.75 Trace Register Map Base Addresses (Hex) Associated Registers 0xE40000-0xE40024 Port 0 Trace Comparison Value 1 and Mask 1 Register 0xE40028-0xE4004C Port 0 Trace Comparison Value 2 and Mask 2 Register 0xE40050-0xE40074 Port 0 Trace Comparison Value 3 and Mask 3 Register 0xE40078-0xE40098 Port 0 Trace Comparison Value 4 and Mask 4 Register 0xE40100-0xE40198...

  • Page 125: Error Registers

    IDT Registers 10.12 ERROR REGISTERS 10.12.1 Error Capability Register (ERR_CAP_REG) Table 10.76 ERR_CAP_REG 0xFD0000 Reset Field Name Type Comment Value ALL_FLAG_STOP 0 = When all error flags are asserted stop the Error Management block and NOP 1 = When all error flags are asserted stop the Error Management function and generate a Maintenance Packet.

  • Page 126: Table 10.78 Special_Err Register Map

    IDT Registers 10.12.3 Special Error Register Table 10.78 SPECIAL_ERR Register Map Base Address (Hex) Associated Registers 0xFD0008 SPECIAL_ERR_REG_0 0xFD000C SPECIAL_ERR_REG_1 0xFD0010 SPECIAL_ERR_REG_2 0xFD0014 SPECIAL_ERR_REG_3 0xFD0018 SPECIAL_ERR_REG_4 0xFD0020 SPECIAL_ERR_REG_5 0xFD0024 SPECIAL_ERR_REG_6 0xFD0028 SPECIAL_ERR_REG_7 Table 10.79 SPECIAL_ERR_0 0xFD0008 Reset Field Name Type Comment Value 3 - 0...

  • Page 127: Table 10.80 Err_Flag 0Xfd0028

    IDT Registers Table 10.79 SPECIAL_ERR_0 0xFD0008 Reset Field Name Type Comment Value ERROR_GROUP_MASK 0 = compare the error group 1 = do not compare the error group ERROR_SOURCE_MASK 0 = compare the error source 1 = do not compare the error source 31 - 23 Reserved...

  • Page 128: Table 10.81 Err_Counter 0Xfd002C

    IDT Registers 10.12.5 Error Counter (ERR_COUNTER) Table 10.81 ERR_COUNTER 0xFD002C Reset Field Name Type Comment Value 15 - 0 COUNT 0x00 The error count 31 - 16 Reserved 10.12.6 Error Reset (ERR_RESET) Table 10.82 ERR_RESET 0xFD0030 Reset Field Name Type Comment Value Reserved...

  • Page 129: Quad Control Registers

    IDT Registers 10.13 QUAD CONTROL REGISTERS Table 10.83 QUAD_CTRL Control Registers Base Address (hex) Associated Registers 0xFF0000-0xFF0004 QUAD_0_CTRL, QUAD_0_ERROR_REPORT_EN 0xFF1000-0xFF1004 QUAD_1_CTRL, QUAD_1_ERROR_REPORT_EN 0xFF2000-0xFF2004 QUAD_2_CTRL, QUAD_2_ERROR_REPORT_EN 0xFF3000-0xFF3004 QUAD_3_CTRL, QUAD_3_ERROR_REPORT_EN 0xFF4000-0xFF4004 QUAD_4_CTRL, QUAD_4_ERROR_REPORT_EN 0xFF5000-0xFF5004 QUAD_5_CTRL, QUAD_5_ERROR_REPORT_EN 0xFF6000-0xFF6004 QUAD_6_CTRL, QUAD_6_ERROR_REPORT_EN 0xFF7000-0xFF7004 QUAD_7_CTRL, QUAD_7_ERROR_REPORT_EN 0xFF8000-0xFF8004 QUAD_8_CTRL, QUAD_8_ERROR_REPORT_EN 0xFF9000-0xFF9004...
  • Page 130 IDT Registers Table 10.84 QUAD_0_CTRL 0xFF0000 Reset Field Name Type Comment Value STD_ENH_SEL 0 = standard 1 = enhanced FORCE_REINIT 1 = Force Reinit 0 = don’t initialize 9 - 7 TXDRVSEL 0b010 Transmitter Drive Strength 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum PLL_LANE_0_1_...

  • Page 131: Table 10.85 Quad_0_Err_Report_En 0Xff0004

    IDT Registers Table 10.84 QUAD_0_CTRL 0xFF0000 Reset Field Name Type Comment Value 25:23 LANE23_TXDRV 0b010 Transmitter Drive Strength for Lanes 2 and 3. Only active if [16] = 1 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum 31 - 26 Reserved...
  • Page 132 IDT Registers Table 10.86 QUAD_CTRL_BROADCAST 0xFFF000 Reset Field Name Type Comment Value STD_ENH_SEL 0 = standard 1 = enhanced FORCE_REINIT 1 = Force Reinit 0 = don’t initialize 9 - 7 TXDRVSEL 0b010 Transmitter Drive Strength 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum PLL_LANE_0_1_RESET...
  • Page 133 IDT Registers Table 10.86 QUAD_CTRL_BROADCAST 0xFFF000 Reset Field Name Type Comment Value 25:23 LANE23_TXDRVSEL 0b010 Transmitter Drive Strength for Lanes 2 and 3. Only active if [16] = 1 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum 31 - 12 Reserved...

  • Page 134: References

    Chapter 11 References 11 REFERENCES For additional detail, the reader is encouraged to consult the following documents: 1) RapidIO Interconnect Specification, Part 1: Input/Output Logical Specification, Rev. 1.3 2) RapidIO Interconnect Specification, Part 2: Message Passing Logical Specification, Rev. 1.3 3) RapidIO Interconnect Specification, Part 3: Common Transport Specification, Rev.
  • Page 135 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 email: srio@idt.com San Jose, CA 95138 www.idt.com phone: 408-360-1533 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products.

  • Page 136: Corporate Headquarters

    Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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