Renesas Y-ASI4U-V5-DB Hardware User Manual
Renesas Y-ASI4U-V5-DB Hardware User Manual

Renesas Y-ASI4U-V5-DB Hardware User Manual

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Y-ASI4U-V5-DB
Hardware User Manual
Introduction
This document explains the hardware design of the Y-ASI4U-V5-DB, its main features and the necessary
hardware setup in order to implement an ASi-5 slave.
Contents
1.
Overview ................................................................................................................................. 3
1.1
ASI4U-V5 ASSP Features ....................................................................................................................... 3
1.2
Y-ASI4U-V5-DB Capabilities ................................................................................................................... 3
2.
Getting Started ........................................................................................................................ 4
2.1
System Block Diagram ............................................................................................................................ 4
2.2
Default Board Configuration .................................................................................................................... 4
3.
Y-ASI4U-V5-DB Components .................................................................................................. 5
3.1
Power Requirements ............................................................................................................................... 5
3.1.1
Power Supply Options ........................................................................................................................... 5
3.1.2
DC/DC Passive Power Supply .............................................................................................................. 6
3.1.3
Renesas ASi-5 Slave Power Supply Reference ................................................................................... 8
3.1.4
Analog/Digital Decoupling ..................................................................................................................... 9
3.1.5
Power Up Behaviour ........................................................................................................................... 10
3.2
Firmware Update Probe connectors...................................................................................................... 10
3.2.1
RL78 Firmware Update Connector...................................................................................................... 10
3.2.2
MIPI20 Debug Connector .................................................................................................................... 10
3.3
Communication Interfaces ..................................................................................................................... 10
3.3.1
CN9 to the ASi Line ............................................................................................................................. 10
3.3.2
Parallel Connector for GPIO access ................................................................................................... 11
3.3.3
PMOD Connector for SPI access ........................................................................................................ 12
3.4
UART Connector ................................................................................................................................... 12
3.4.1
3.5mm Audio Jack Connector ............................................................................................................. 12
3.4.2
UART Access ...................................................................................................................................... 13
3.5
LEDs ...................................................................................................................................................... 13
3.5.1
RL78 Status LEDs ............................................................................................................................... 13
3.5.2
I/O Status LEDs ................................................................................................................................... 15
3.5.3
Power Status LED ............................................................................................................................... 15
3.6
Under Voltage Detection Circuit ............................................................................................................ 15
3.7
Reset Circuit .......................................................................................................................................... 15
3.7.1
Push Button ......................................................................................................................................... 15
R12AN0109ED0100 Rev.1.30
January.14.22
Hardware User Manual
Page 1 of 24

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Summary of Contents for Renesas Y-ASI4U-V5-DB

  • Page 1: Table Of Contents

    Hardware User Manual Y-ASI4U-V5-DB Hardware User Manual Introduction This document explains the hardware design of the Y-ASI4U-V5-DB, its main features and the necessary hardware setup in order to implement an ASi-5 slave. Contents Overview ..........................3 ASI4U-V5 ASSP Features ........................3 Y-ASI4U-V5-DB Capabilities ........................
  • Page 2 3.10.1 PCB Manufacturing Characteristics ....................18 3.10.2 Galvanic Isolation ..........................19 3.10.3 Ground Connection ..........................19 3.10.4 Y-ASI4U-V5-DB Layout ........................20 Revision History ..........................24 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products ..1 Notice ............................. 1 R12AN0109ED0100 Rev.1.30...
  • Page 3: Overview

    Package: 64-pin Quad Flat No-lead (QFN), 9 x 9 mm, 0.5 mm pitch For more information, please refer to the ASI4U-V5 ASSP Datasheet. 1.2 Y-ASI4U-V5-DB Capabilities The Y-ASI4U-V5-DB integrates all the necessary components in order to quickly evaluate the ASi-5 Fieldbus technology. Figure 1: Y-ASI4U-V5-DB picture R12AN0109ED0100 Rev.1.30...
  • Page 4: Getting Started

    Jack LEDs Figure 2: Y-ASI4U-V5-DB block diagram 2.2 Default Board Configuration Make sure that the provided cable set (brown and blue) is connected from CN11 to the DC/DC Module power input. Also, close CN12, to enable the DC/DC Module to produce the 5 and 3.3 Volts from the ASi line voltage.
  • Page 5: Y-Asi4U-V5-Db Components

    3.1.1.1 Option 1A: CN9 Connector The CN9 is a male right-angle 4-pin M12-A-coded connector. It enables an easy connection between the Y-ASi4U-V5-DB and the ASi line. From this connector, only 2 pins are used to connect to the ASi signal and the power supply.
  • Page 6: Option 3: Cn27 Connector

    Figure 7: CN27 connector 3.1.2 DC/DC Passive Power Supply Here is the schematic of the DC/DC Module mounted on connector CN26 of the Y-ASI4U-V5-DB. This is a passive components-based isolated power supply containing a shut-down and auto-recovery short circuit protection feature.
  • Page 7 Y-ASI4U-V5-DB Hardware User Manual Figure 8: Onboard DC/DC schematic Figure 9: Onboard DC/DC picture R12AN0109ED0100 Rev.1.30 Page 7 of 24 January.14.22...
  • Page 8: Renesas Asi-5 Slave Power Supply Reference

    Y-ASI4U-V5-DB Hardware User Manual 3.1.3 Renesas ASi-5 Slave Power Supply Reference In order to replace the existing DC/DC module assembled on connector CN26. Renesas recommends the 2 following designs: These were implemented according to the 2 following use cases: •...
  • Page 9: Analog/Digital Decoupling

    Here is the Evaluation Board: Figure 11: RTKA_ASI5ISOPOWSUP1Z EVB All documents can be found under the folder: Y-ASI4U-V5-DB\HW\ASI5_Power_Supply\Isolated Please check with your Renesas representative or the Renesas website on how to obtain the RTKA_ASI5ISOPOWSUP1Z evaluation board. 3.1.3.2 Non-isolated PSU Renesas recommends using the following configuration to provide the necessary voltage to power the ASSP.
  • Page 10: Power Up Behaviour

    Use a Renesas Debug probe in order to update the Firmware the ASI4U-V5_ASSP. We recommend using the “Renesas E2 lite” for this operation; Please check with your Renesas representatives or the Renesas website on how the probe can be obtained.
  • Page 11: Parallel Connector For Gpio Access

    Simple or Complex slave use case. The SPI interface can also be accessed via CN14 enabling an easy and unique cabling for both modes. Slave Figure 15: ASi-5 to Multisensorboard parallel connector Mapping of ASI4U-V5_ASSP signals/voltages to the Y-Multisensorboard_1: Y-ASI4U-V5-DB CN14 ASI4U-V5_ASSP Y-Multisensorboard_1 J33 P0_00 BIT0...
  • Page 12: Pmod Connector For Spi Access

    Y-ASI4U-V5-DB Hardware User Manual P1_00 BIT16 P1_01 BIT17 / SPI CLK P1_02 BIT18 / SPI MOSI P1_03 BIT19 / SPI MISO P1_04 BIT20 / SPI SS P1_05* BIT23 / UART0 RX/TX P1_06 BIT22 (DSR signal) Figure 16: Parallel connector pin mapping *Note: P1_05 can be accessed on BIT23 and via the UART Connector.
  • Page 13: Uart Access

    Y-ASI4U-V5-DB Hardware User Manual 3.4.1.1 VCP-HH5-01 Bluetooth Addresser ASi-5 offers the possibility for the Master to configure the slave address and other parameters directly. Alternatively, ASi-5 slaves can be configured using an ASi-5 addresser tool in combination with an ASi-5 addresser app.
  • Page 14 Y-ASI4U-V5-DB Hardware User Manual Figure 20: RL78 Status LEDs • RP7_0 and RP7_1 are the status LEDs related to the table page 10 of the “ASi5- Device_ImplementationGuide.pdf” • RP4_0 lights ON when the RL78 NVRAM content is written by the probe.
  • Page 15: I/O Status Leds

    Y-ASI4U-V5-DB Hardware User Manual 3.5.2 I/O Status LEDs The following LEDs can be used to monitor the output signals of P0_00...P0_07. Figure 22: I/O status LEDs These 8 LEDs can be used to visualize the outputs of P0_00...P0_07 in the case these GPIOs are configured as outputs.
  • Page 16: Reset Monitoring Ic

    Y-ASI4U-V5-DB Hardware User Manual 3.7.2 Reset Monitoring IC The following circuit is used to send a clean logical signal to the ASI4U-V5_ASSP when SW1 is pressed. Figure 24: Reset monitoring IC 3.8 Analog Front End coupling/Decoupling Circuit The Analog Front End (AFE) of the ASi-5 Slave with the external decoupling unit and supply of the ASI4U- V5_ASSP is shown below.
  • Page 17: Transformer Dimensions

    • WE 750316410 from Würth Electronics. Figure 26: WE 750316410 spec 3.8.2 Coils Dimensions Here is the specification of the coil used for the Y-ASI4U-V5-DB design: • WE 744776381 Figure 27: WE 744776381 spec Depending on hardware characteristics, additional series inductances may be needed to ensure that the...
  • Page 18: Asi4U-V5 Assp

    AFE conversion highly depends on the precision of these voltage references. 3.10 PCB Characteristics 3.10.1 PCB Manufacturing Characteristics The Y-ASI4U-V5-DB is a 4-layer PCB. The following table represents the PCB manufacturing characteristics of the board regarding the cooper and dielectric thickness: Figure 30: PCB manufacturing spec Such parameters must be adapted according to your hardware design and requirements in order to respect the Impedance and Symmetry specification values.
  • Page 19: Galvanic Isolation

    ASI4U-V5_ASSP is ensured by the DC/DC’s transformer T1 (See schematic chapter 3.1.2). 3.10.3 Ground Connection On the Y-ASI4U-V5-DB, all the AFE and digital related grounds are connected between each other with R30, R95 and R96. Figure 31: Ground connection of the different power rails R12AN0109ED0100 Rev.1.30...
  • Page 20: Y-Asi4U-V5-Db Layout

    Y-ASI4U-V5-DB Hardware User Manual 3.10.4 Y-ASI4U-V5-DB Layout TOP LAYER: R12AN0109ED0100 Rev.1.30 Page 20 of 24 January.14.22...
  • Page 21 Y-ASI4U-V5-DB Hardware User Manual GND LAYER: R12AN0109ED0100 Rev.1.30 Page 21 of 24 January.14.22...
  • Page 22 Y-ASI4U-V5-DB Hardware User Manual POWER LAYER: R12AN0109ED0100 Rev.1.30 Page 22 of 24 January.14.22...
  • Page 23 Y-ASI4U-V5-DB Hardware User Manual BOTTOM LAYER: R12AN0109ED0100 Rev.1.30 Page 23 of 24 January.14.22...
  • Page 24: Revision History

    Y-ASI4U-V5-DB Hardware User Manual Revision History Description Rev. Date Page Summary 05.05.20 Release 28.07.20 Update Isolated PSU EVB reference 27.10.20 Impedance/Symmetry described in a separated document 14.01.22 Update NON isolated PSU reference due to EOL R12AN0109ED0100 Rev.1.30 Page 24 of 24...
  • Page 25: General Precautions In The Handling Of Microprocessing Unit And Microcontroller Unit Products

    Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
  • Page 26: Notice

    Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.

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