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EVBUM2284/D
KLI-4104 Imager Board
User's Manual
Description
The KLI−4104 Imager Evaluation Board, referred to in
this document as the Imager Board, is designed to be used
as part of a two−board set, used in conjunction with a Timing
Generator Board. ON Semiconductor offers an Imager
Board / Timing Generator Board package that has been
designed and configured to operate with the KLI−4104
Image Sensors.
The Timing Generator Board generates the timing signals
necessary to operate the CCD, and provides the power
required by the Imager Board. The timing signals, in LVDS
format, and the power, are provided to the Imager Board via
the interface connector (J5). In addition, the Timing
Generator Board performs the processing and digitization of
the analog video output of the Imager Board.
The KLI−4104 Imager Board has been designed to
operate the KLI−4104 with the specified performance at
Table 1. POWER REQUIREMENTS
Power Supplies
+5 V_MTR Supply
−5 V_MTR Supply
VPLUS Supply
Total Power Dissipation
Table 2. SIGNAL LEVEL REQUIREMENTS
Input Signals (LVDS)
H1A (±)
H1B (±)
H2A (±)
H2B (±)
FDG
R (±)
V1 (±)
V2 (±)
V2B (±)
V3RD (±)
VES (±)
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 2
INPUT REQUIREMENTS
Minimum
Typical
4.9
5.0
1.3
−5.1
−5.0
0.2
18
20
1.8
42
V
V
min
threshold
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
EVAL BOARD USER'S MANUAL
30 MHz pixel clocking rate and nominal operating
conditions. (See the KLI−4104 performance specifications
for details).
For testing and characterization purposes, the KLI−4104
Imager board provides the ability to adjust many of the CCD
bias voltages and CCD clock level voltages by adjusting
potentiometers on the board. The Imager Board provides the
means to modify other device operating parameters (e.g.,
CCD Reset clock pulse width, Input Diode clock pulse
width) by populating components differently on the board.
Maximum
Units
5.1
V
A
−4.9
V
A
21
V
A
W
V
Units
max
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
1
www.onsemi.com
Comments
Air cooling recommended
Comments
H1 clock
ID clock
H2 clock
(not used)
LOGR clock
Reset clock
TG1 clock
TG2 clock
LOGB clock
LOGG clock
LOGL clock
Publication Order Number:
EVBUM2284/D

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Summary of Contents for ON Semiconductor KLI-4104

  • Page 1 Imager Board, is designed to be used www.onsemi.com as part of a two−board set, used in conjunction with a Timing Generator Board. ON Semiconductor offers an Imager EVAL BOARD USER’S MANUAL Board / Timing Generator Board package that has been designed and configured to operate with the KLI−4104...
  • Page 2 H1L CCD Timing Adjustment Potentiometers Optional DAC Input Connector (P1) Minor timing adjustments can be made to the H1L CCD The P1 connector is provided for ON Semiconductor test right and left clock positions using the delay adjust purposes, and is not populated.
  • Page 3 EVBUM2284/D KLI−4104 OPERATIONAL SETTINGS The Imager board is configured to operate the KLI−4104 were correct at the time of this document’s publication, but Image Sensors under the following operating conditions: may be subject to change; refer to the KLI−4104 device specification.
  • Page 4 The pulse width of ID_CCD is set by configuring P[2..0], populating the resistors R193−196 accordingly. This circuit the inputs to the programmable one−shot U49. P[2..0] can be is provided for ON Semiconductor test purposes only. Table 6. ID CLOCK PULSE WIDTH Pulse Width...
  • Page 5: Block Diagram And Performance Data

    EVBUM2284/D BLOCK DIAGRAM AND PERFORMANCE DATA LINE EMITTER DRIVER FOLLOWER LINE GREEN EMITTER DRIVER FOLLOWER LINE EMITTER DRIVER FOLLOWER LINE EMITTER DRIVER FOLLOWER LINE EMITTER DRIVER FOLLOWER LINE LINE BLUE EMITTER EMITTER DRIVER DRIVER FOLLOWER FOLLOWER CCD BIAS VOLTAGE ADJUSTMENT POTS: RCLK RCLK TG1L, IG, OG, LS, RD...
  • Page 6 EVBUM2284/D LINEARITY 100000 10000 1000 MEASURED %DEVIATION FROM FIT 0.01 0.0001 0.001 0.01 INTEGRATION TIME (SECONDS) Figure 2. Measured Performance − Linearity (Luma Channel) Photon Transfer Slope = el/Adu = 16.58 electrons Noise floor = 1.79 counts (29.7 electrons) LVSAT = 47883 electrons VSAT = 64248 electrons 1000 10000...
  • Page 7: Connector Assignments And Pinouts

    EVBUM2284/D CONNECTOR ASSIGNMENTS AND PINOUTS Video Out SMB Connectors The emitter−follower buffered CCD_VOUT signals are impedance of 75 W should be used to connect the imager driven from the Imager Board via the SMB connectors J1, board to the Timing Generator Board to match the series and J2, J3, J4, J6, J7, and J8.
  • Page 8 Timing Board before power is applied. If the Imager Board is connected to the Timing ON Semiconductor reserves the right to change any Board during the reprogramming of the Altera PLD, damage information contained...
  • Page 9: Additional Information

    onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.

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