ON Semiconductor KAI-4011 User Manual

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EVBUM2279/D
KAI-4011 / KAI-4021 /
KAI-04022 Imager Board
User's Manual
Description
The
KAI−4011 / KAI−4021 / KAI−04022
Evaluation Board, referred to in this document as the Imager
Board, is designed to be used as part of a two−board set, used
in conjunction with a Timing Generator Board.
ON Semiconductor offers an Imager Board / Timing
Generator Board package that has been designed and
configured to operate with the KAI−4011 / KAI−4021 /
KAI−04022 Image Sensors.
The Timing Generator Board generates the timing signals
necessary to operate the CCD, and provides the power
required by the Imager Board. The timing signals, in LVDS
format, and the power, are provided to the Imager Board via
the interface connector (J1). In addition, the Timing
Generator Board performs the processing and digitization of
the analog video output of the Imager Board.
The KAI−4011 / KAI−4021 / KAI−04022 Imager Board
has been designed to operate the KAI−4011 / KAI−4021 /
Table 1. POWER REQUIREMENTS
Power Supplies
+5 V_MTR Supply
−5 V_MTR Supply
VPLUS Supply
VMINUS Supply
Table 2. SIGNAL LEVEL REQUIREMENTS
Input Signals (LVDS)
H1A (±)
H1B (±)
H2A (±)
H2B (±)
FDG
R (±)
V1 (±)
V2 (±)
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 2
Imager
INPUT REQUIREMENTS
Minimum
Typical
4.9
−5.1
18
−21
V
V
min
threshold
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
0
±0.1
EVAL BOARD USER'S MANUAL
KAI−04022 CCDs with the specified performance at
40 MHz pixel clocking rate and nominal operating
conditions. (See the KAI−4011 / KAI−4021 / KAI−04022
performance specifications for details).
For testing and characterization purposes, the KAI−4011 /
KAI−4021 / KAI−04022 Imager board provides the ability
to adjust many of the CCD bias voltages and CCD clock
level voltages by adjusting potentiometers on the board. The
Imager Board provides the means to modify other device
operating parameters (CCD reset clock pulse width, VSS
bias voltage) by populating components differently on the
board.
Maximum
5.0
5.1
1400
−5.0
−4.9
200
20
21
175
−20
−18
150
V
Units
max
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
2.4
V
1
www.onsemi.com
Units
V
mA
V
mA
V
mA
V
mA
Comments
H1A clock
H1B clock
H2A clock
H2B clock
Fast Dump clock
Reset clock
V1 clock
V2 clock
Publication Order Number:
EVBUM2279/D

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Summary of Contents for ON Semiconductor KAI-4011

  • Page 1 Board, is designed to be used as part of a two−board set, used in conjunction with a Timing Generator Board. ON Semiconductor offers an Imager Board / Timing Generator Board package that has been designed and KAI−04022 CCDs with the specified performance at configured to operate with the KAI−4011 / KAI−4021 /...
  • Page 2: Architecture Overview

    EVBUM2279/D Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) Units Comments threshold V2B (±) ±0.1 V2B clock V3RD (±) ±0.1 V2 Clock 3 level VES (±) Electronic Shutter ±0.1 AMP_ENABLE (±) ±0.1 Output Amplifier Enable ARCHITECTURE OVERVIEW The following sections describe the functional blocks of frame to transfer the charge from the photodiodes to the the KAI−4011 / KAI−4021 / KAI−04022 Imager Board vertical CCDs.
  • Page 3: Operational Settings

    EVBUM2279/D OPERATIONAL SETTINGS The Imager board is configured to operate the KAI−4011 / were correct at the time of this document’s publication, but KAI−4021 / KAI−04022 Image Sensors under the following may be subject to change; refer to the KAI−4011 / operating conditions: KAI−4021 / KAI−04022 device specification.
  • Page 4: Block Diagram And Performance Data

    EVBUM2279/D BLOCK DIAGRAM AND PERFORMANCE DATA LINE LINE EMITTER EMITTER DRIVER DRIVER FOLLOWER FOLLOWER V3RD DRIVER (optional) VOUT LEFT VOUT RIGHT RCLK RCLK DRIVER 1 SHOT DRIVER CCD SENSOR FDG CKT VES CKT DRIVER DRIVER DRIVER DRIVER DRIVER LVDS TO TTL BUFFERS +15 V REGULATOR LVDS RECEIVERS...
  • Page 5 EVBUM2279/D Photon Transfer Slope = el/Adu = 9.29 electrons Noise floor = 3.65 counts (33.9 electrons) LVSAT = 30220 electrons VSAT = 32980 electrons 1000 10000 100000 Signal Mean (Electrons) Figure 3. Measured Performance − Dynamic Range and Noise Floor http://onsemi.com...
  • Page 6: Connector Assignments And Pinouts

    EVBUM2279/D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J2 and J3 The emitter−follower buffered CCD_VOUT signals are 75 W should be used to connect the imager board to the driven from the Imager Board via the SMB connectors J2 Timing Generator Board to match the series and terminating and J3.
  • Page 7 Timing Board before power is applied. If the Imager Board is connected to the Timing ON Semiconductor reserves the right to change any Board during the reprogramming of the Altera PLD, damage information contained...
  • Page 8: Additional Information

    onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.

This manual is also suitable for:

Kai-4021Kai-04022

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