onsemi NCP51752 Series User Manual

Isolated SiC MOSFET Gate
Driver Evaluation Board
User's Manual
NCP51752 EVBUM
Introduction
This user guide supports the evaluation board for the NCP51752. It
should be used in conjunction with the NCP51752 datasheets as well
as onsemi's application notes and technical support team. Please visit
onsemi's website at www.onsemi.com.
This document describes the proposed solution for an isolated single
channel gate driver using the NCP51752 family. This user's guide also
includes information regarding operating procedures, input/output
connections, an electrical schematic, printed circuit board (PCB)
layout, and a bill of material (BOM) for the evaluation board.
These evaluation boards can be used to evaluate:
•
NCP51752xyDR2G
•
NCV51752xyDR2G
Description
The NCP51752 is a family of isolated single−channel gate driver
with +4.5 A / −9 A source and sink peak current respectively. They are
designed for fast switching to drive power MOSFETs and SiC
MOSFET power switches. The NCP51752 offers short and matched
propagation delays.
For improved reliability, dV/dt immunity and even faster turn−off,
the NCP51752 has an embedded negative bias rail mechanism
between GND2 and VEE pins.
The NCP51752 offers other important protection function such as
independent under−voltage lockout for both−side driver. It's Vcc
UVLO threshold with referenced to GND2 for true UVLO level
regardless of voltage level between GND2 and VEE pin. The
NCP51752 is available in a 4 mm SOIC−8 package and can support
isolation voltage up to 3.75 kV
Key Features
•
Feature Options
V UVLO Referenced to GND2
♦
CC
Built−in Negative Bias between GND2 and V
♦
•
3 V to 20 V Input Supply Voltage
•
Output Supply Voltage from 6.5 V to 30 V with 6 V and 8 V for
MOSFET, 12 V and 17 V for SiC MOSFET, Threshold.
•
4.5 A Peak Source, 9 A Peak Sink Output Current Capability
•
Two Input Configurations with Negative 5 V Handling Capability
on Input Pins
•
Minimum CMTI of 200 V/ns dV/dt
•
Propagation Delay Typical 36 ns with
5 ns Max Delay Matching
♦
•
Available Package Footprint
Type−A : TO−3P, TO−247−3L, D−PAK, and D2PAK
♦
Type−B : TO−247−4L
♦
Type−C : D2PAK−7L
♦
© Semiconductor Components Industries, LLC, 2023
August, 2023 − Rev. 0
.
RMS
pins
EE
EVAL BOARD USER'S MANUAL
Figure 1. Evaluation Board Picture
V
DD
IN+
IN−
GND1
FUNCTIONAL BLOCK DIAGRAM
V
VDDUVLO
DD
IN+
IN+
1
IN−
IN−
GND1
1
1
www.onsemi.com
(A) For TO−247−3L
(B) For D2PAK
Type−A
Type−B
Type−C
PIN CONNECTIONS
V
1 8
EE
GND2
7
NCP51752
OUT
6
V
5
CC
UVLO
DRIVE
PWM
Tx Rx
LOGIC
LOGIC
Negative
Bias
Publication Order Number:
EVBUM2871/D
V
CC
OUT
V
EE
2
GND2