Receiver Circuits - Icom IC-25A Instruction Manual

OUTLINE
The IC-25A/E employs a digital phase locked loop (PLL) circuit as the local oscillator for both
transmit and receive. The output of the PLL circuit is approximately 16.9MHz below the receive
frequency, thereby spurious is kept to a minimum.
The operating frequency is controlled by pulse signals, generated by the rotary encoder located at
the tuning knob, being added to or subtracted from the preset frequencies in the microcomputer.
The microcomputer controls the PLL circuit which determines the output frequency of the VCO
(Voltage Controlled Oscillator). |
In the receiver section, signals from the antenna аге mixed with the local oscillator output from
the PLL circuit. The circuits function as a dual-conversion type with 16.9MHz 1st IF and 455KHz
2nd IF. |
In the transmitter section, a crystal oscillator is used to produce the 16.9MHz signals which аге
direct-frequency modulated.
The FM signal is mixed with the local oscillator output from the PLL circuit, which is the same as
that of the receiver section, and then amplified, filtered, and sent to the antenna.
RECEIVER CIRCUITS
ANTENNA SWITCHING CIRCUIT
Signals from the antenna connector are fed to the RF amplifier Q3 in the MAIN unit through low-
pass filters in the PA unit. The switching diodes D1 and D2 in the PA unit, are turned OFF in the
receive mode, and isolate the PA module from the receiver circuit.
RF CIRCUIT
The signals from the PA unit, are amplified by the low-noise MOS FET Q3 and then sent to the
four-stage helical cavity filter, which reduces interference and intermodulation from other radio
signals or nearby signals. The filtered signals are then fed to one of the ports of the double bal-
anced mixer (DBM) consisting of four Schottky diodes, D3 — D6.
To another port of the DBM, a 127MHz signal is supplied from the PLL unit to convert the RF
signals into first IF signals.
RF CIRCUIT
144.00
16.9MHZ
127.1
129.09 MHZ
PLL UNIT
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