Driver Circuit - Icom IC-25A Instruction Manual

O6 81, B2
When this flow occurs, the offset frequency is preset for 600K Hz.
FREQUENCY CONTROL, DISPLAY AND 1/0 CIRCUIT
When the power is turned ON, the CPU is initialized and then reads the mode setting and memo-
rizes it. Then the CPU reads the control data from the external controller in the order of the
numbers of the matrix and controls the various necessary operations. The data of the display, "А"
VFO, "B" VFO, the frequency shift, step pitch, Memories 1 ~ 5, and the divide number (N) are
programmed in each RAM area for the initial presetting.
Then, at the CPU output terminals EO ~ ЕЗ, the divide number and the 5KHz shift data are put
out in the BCD code. The data to designate the latch position (digit-position) are output at the
CPU output DO — D3 and the signals from G3 are latched as the strobe pulse in the PLL IC.
DRIVER CIRCUIT
DECIMAL DIGIT SEGMENT
FRONT
P
=
FRONT
OINT CONT.
CONTRO
CONTROL
1
|
ОАТА
55 | ОСАМ
SWITCH
CLOCK OSC.
SCAN
INPUT
|
|
|
PRIORITY
CONTROL
|
UP/DOWN
DIGIT
PRI
PRIORITY
TP
ЗАВ
SWITCH
|
CLOCK OSC.
CONTROL
ROTALY ү
ENCODER
|
INPUT
ATRIX
|
ин
м
CJ 400KHZ
| COUNTER
|
|
FUNCTION |
SWITCH |
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