Renesas RA2L1 R7FA2L1AB3CNE Manuals

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Renesas RA2L1 R7FA2L1AB3CNE User Manual

Renesas RA2L1 R7FA2L1AB3CNE User Manual (1117 pages)

Brand: Renesas | Category: Microcontrollers | Size: 11 MB

Table of Contents

Corporate Headquarters
2
Contact Information
2
General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
3
About this Document
4
Typographic Notation
5
Special Terms
5
Register Description
6
Proprietary Notice
8
Table of Contents
9
Features
39
Overview
40
Function Outline
40
Block Diagram
44
Part Numbering
44
Function Comparison
47
Pin Functions
48
Pin Assignments
51
Pin Lists
54
Cpu
58
Overview
58
Debug
58
Operating Frequency
58
Block Diagram
58
Implementation Options
59
SWD Interface
60
Debug Function
60
Debug Mode Definition
60
Debug Mode Effects
60
Low Power Mode
60
Programmers Model
61
Address Spaces
61
Cortex-M23 Peripheral Address Map
62
External Debug Address Map
62
Coresight ROM Table
62
DBGREG Module
63
OCDREG Module
65
Systick Timer
67
OCD Emulator Connection
67
Unlock ID Code
68
Dbgen
68
Restrictions on Connecting an OCD Emulator
68
References
70
Usage Notes
70
Operating Modes
71
Operating Mode Types and Selection
71
Details of Operating Modes
71
Single-Chip Mode
71
SCI Boot Mode
71
Operating Modes Transitions
71
Operating Mode Transitions as Determined by the Mode-Setting Pin
71
Address Space
72
Resets
73
Overview
73
Register Descriptions
78
RSTSR0 : Reset Status Register 0
78
RSTSR1 : Reset Status Register 1
79
RSTSR2 : Reset Status Register 2
81
Operation
82
RES Pin Reset
82
Power-On Reset
82
Voltage Monitor Reset
83
Independent Watchdog Timer Reset
84
Watchdog Timer Reset
84
Software Reset
85
Determination of Cold/Warm Start
85
Determination of Reset Generation Source
85
Usage Notes
86
Note on RES Pin Reset
86
Option-Setting Memory
87
Overview
87
Register Descriptions
87
OFS0 : Option Function Select Register 0
87
OFS1 : Option Function Select Register 1
91
MPU Registers
92
AWS : Access Window Setting Register
93
OSIS : Ocd/Serial Programmer ID Setting Register
94
Setting Option-Setting Memory
95
Allocation of Data in Option-Setting Memory
95
Setting Data for Programming Option-Setting Memory
95
Usage Notes
96
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory
96
Note on FSPR Bit
96
Low Voltage Detection (LVD)
97
Overview
97
Register Descriptions
99
LVCMPCR : Voltage Monitor Circuit Control Register
99
LVDLVLR : Voltage Detection Level Select Register
100
LVD1CR0 : Voltage Monitor 1 Circuit Control Register 0
100
LVD2CR0 : Voltage Monitor 2 Circuit Control Register 0
101
LVD1CR1 : Voltage Monitor 1 Circuit Control Register
102
LVD1SR : Voltage Monitor 1 Circuit Status Register
102
LVD2CR1 : Voltage Monitor 2 Circuit Control Register 1
103
LVD2SR : Voltage Monitor 2 Circuit Status Register
103
VCC Input Voltage Monitor
104
Monitoring Vdet0
104
Monitoring Vdet1
104
Monitoring Vdet2
104
Reset from Voltage Monitor 0
105
Interrupt and Reset from Voltage Monitor 1
105
Interrupt and Reset from Voltage Monitor 2
107
Event Link Controller (ELC) Output
109
Interrupt Handling and Event Linking
109
Usage Notes
110
Note on Voltage Detection 1 Level Select
110
Clock Generation Circuit
111
Overview
111
Register Descriptions
113
SCKDIVCR : System Clock Division Control Register
114
SCKSCR : System Clock Source Control Register
115
MEMWAIT : Memory Wait Cycle Control Register for Code Flash
115
FLDWAITR : Memory Wait Cycle Control Register for Data Flash
116
MOSCCR : Main Clock Oscillator Control Register
119
SOSCCR : Sub-Clock Oscillator Control Register
120
LOCOCR : Low-Speed On-Chip Oscillator Control Register
121
HOCOCR : High-Speed On-Chip Oscillator Control Register
121
MOCOCR : Middle-Speed On-Chip Oscillator Control Register
122
OSCSF : Oscillation Stabilization Flag Register
123
OSTDCR : Oscillation Stop Detection Control Register
124
OSTDSR : Oscillation Stop Detection Status Register
125
MOSCWTCR : Main Clock Oscillator Wait Control Register
125
MOMCR : Main Clock Oscillator Mode Oscillation Control Register
126
SOMCR : Sub-Clock Oscillator Mode Control Register
127
SOMRG : Sub-Clock Oscillator Margin Check Register
127
CKOCR : Clock out Control Register
128
LOCOUTCR : LOCO User Trimming Control Register
129
MOCOUTCR : MOCO User Trimming Control Register
129
HOCOUTCR : HOCO User Trimming Control Register
130
Main Clock Oscillator
130
Connecting a Crystal Resonator
130
External Clock Input
131
Notes on External Clock Input
131
Sub-Clock Oscillator
131
Connecting a 32.768-Khz Crystal Resonator
132
Pin Handling When the Sub-Clock Oscillator Is Not Used
132
Oscillation Stop Detection Function
133
Oscillation Stop Detection and Operation after Detection
133
Oscillation Stop Detection Interrupts
134
Internal Clock
135
System Clock (ICLK)
135
Peripheral Module Clock (PCLKB, PCLKD)
136
CAN Clock (CANMCLK)
136
CAC Clock (CACCLK)
136
RTC-Dedicated Clock (RTCSCLK, RTCS128CLK, RTCLCLK)
137
IWDT-Dedicated Clock (IWDTCLK)
137
AGT-Dedicated Clock (AGTSCLK, AGTLCLK)
137
Systick Timer-Dedicated Clock (SYSTICCLK)
137
External Pin Output Clock (CLKOUT)
137
Usage Notes
137
Notes on Clock Generation Circuit
137
Notes on Resonator
138
Notes on Board Design
138
Notes on Resonator Connect Pin
138
Clock Frequency Accuracy Measurement Circuit (CAC)
139
Overview
139
Register Descriptions
140
CACR0 : CAC Control Register 0
140
CACR1 : CAC Control Register 1
141
CACR2 : CAC Control Register 2
141
CAICR : CAC Interrupt Control Register
142
CASTR : CAC Status Register
143
CAULVR : CAC Upper-Limit Value Setting Register
144
CALLVR : CAC Lower-Limit Value Setting Register
145
CACNTBR : CAC Counter Buffer Register
145
Operation
145
Measuring Clock Frequency
145
Digital Filtering of Signals on CACREF Pin
147
Interrupt Requests
147
Usage Notes
147
Settings for the Module-Stop Function
147
Low Power Modes
148
Overview
148
Register Descriptions
151
SBYCR : Standby Control Register
151
MSTPCRA : Module Stop Control Register a
152
MSTPCRB : Module Stop Control Register B
152
MSTPCRC : Module Stop Control Register C
153
MSTPCRD : Module Stop Control Register D
154
OPCCR : Operating Power Control Register
155
SOPCCR : Sub Operating Power Control Register
156
SNZCR : Snooze Control Register
157
SNZEDCR0 : Snooze End Control Register 0
158
SNZREQCR0 : Snooze Request Control Register 0
159
PSMCR : Power Save Memory Control Register
161
SYOCDCR : System Control OCD Control Register
161
DCDCCTL : DCDC/LDO Control Register
162
VCCSEL : Voltage Level Selection Control Register
162
LSMRWDIS : Low Speed Module R/W Disable Control Register
163
LPOPT : Lower Power Operation Control Register
164
Reducing Power Consumption by Switching Clock Signals
165
Module-Stop Function
165
Function for Lower Operating Power Consumption
165
Setting Operating Power Control Mode
165
Low Power Modes
167
Operating Range
168
High-Speed Mode
168
Sleep Mode
170
Transitioning to Sleep Mode
170
Canceling Sleep Mode
171
Software Standby Mode
172
Transition to Software Standby Mode
172
Canceling Software Standby Mode
172
Example of Software Standby Mode Application
173
Snooze Mode
173
Transition to Snooze Mode
173
Canceling Snooze Mode
174
Returning from Snooze Mode to Software Standby Mode
175
Snooze Operation Example
176
Usage Notes
180
Register Access
180
I/O Port Pin States
181
Module-Stop State of DTC
181
Internal Interrupt Sources
181
Transitioning to Low Power Modes
181
Timing of WFI Instruction
181
Writing to the WDT/IWDT Registers by DTC in Sleep Mode or Snooze Mode
181
Oscillators in Snooze Mode
181
Snooze Mode Entry by RXD0 Falling Edge
181
Using UART of SCI0 in Snooze Mode
182
Conditions of A/D Conversion Start in Snooze Mode
182
Conditions of CTSU in Snooze Mode
182
ELC Events in Snooze Mode
182
Module-Stop Function for ADC120
182
Module-Stop Function for an Unused Circuit
182
Register Write Protection
184
Overview
184
Register Descriptions
184
PRCR : Protect Register
184
Interrupt Controller Unit (ICU)
185
Overview
185
Register Descriptions
186
Irqcri : IRQ Control Register (I = 0 to 7)
186
NMISR : Non-Maskable Interrupt Status Register
187
NMIER : Non-Maskable Interrupt Enable Register
190
NMICLR : Non-Maskable Interrupt Status Clear Register
192
NMICR : NMI Pin Interrupt Control Register
193
Ielsrn : ICU Event Link Setting Register N (N = 0 to 31)
194
SELSR0 : SYS Event Link Setting Register
195
WUPEN : Wake up Interrupt Enable Register
196
IELEN : ICU Event Enable Register
198
Vector Table
198
Interrupt Vector Table
198
Event Number
199
ICU and DTC Event Number
204
Interrupt Operation
210
Detecting Interrupts
210
Interrupt Setting Procedure
211
Enabling Interrupt Requests
211
Disabling Interrupt Requests
211
Polling for Interrupts
211
Selecting Interrupt Request Destinations
212
DTC Activation
212
Digital Filter
212
External Pin Interrupts
213
Non-Maskable Interrupt Operation
213
Return from Low Power Modes
214
Return from Sleep Mode
214
Return from Software Standby Mode
214
Return from Snooze Mode
214
Using the WFI Instruction with Non-Maskable Interrupts
215
Reference
215
Buses
216
Overview
216
Description of Buses
217
Main Buses
217
Slave Interface
217
Parallel Operations
217
Restriction on Endianness
217
Register Descriptions
218
Busmcntx : Master Bus Control Register X (X = SYS, DMA)
218
Busnerradd : Bus Error Address Register N (N = 3, 4)
218
Busnerrstat : BUS Error Status Register N (N = 3, 4)
219
Bus Error Monitoring Section
219
Error Type that Occurs by Bus
219
Operation When a Bus Error Occurs
219
Conditions for Issuing Illegal Address Access Errors
220
References
220
Memory Protection Unit (MPU)
221
Overview
221
CPU Stack Pointer Monitor
221
Protecting the Registers
224
Overflow and Underflow Errors
224
Register Descriptions
224
Arm MPU
228
Bus Master MPU
228
Register Descriptions
230
Operation
234
Bus Slave MPU
236
Register Descriptions
237
Functions
242
Security MPU
243
Register Descriptions (Option-Setting Memory)
243
Memory Protection
248
Usage Notes
249
Notes on the Use of a Debugger
249
References
249
Data Transfer Controller (DTC)
251
Overview
251
Register Descriptions
252
MRA : DTC Mode Register a
252
MRB : DTC Mode Register B
253
SAR : DTC Transfer Source Register
254
DAR : DTC Transfer Destination Register
255
CRA : DTC Transfer Count Register a
255
CRB : DTC Transfer Count Register B
256
DTCCR : DTC Control Register
256
DTCVBR : DTC Vector Base Register
256
DTCST : DTC Module Start Register
257
DTCSTS : DTC Status Register
257
Activation Sources
258
Allocating Transfer Information and DTC Vector Table
258
Operation
260
Transfer Information Read Skip Function
262
Transfer Information Write-Back Skip Function
262
Normal Transfer Mode
263
Repeat Transfer Mode
264
Block Transfer Mode
265
Chain Transfer
266
Operation Timing
267
Execution Cycles of DTC
269
DTC Bus Mastership Release Timing
270
DTC Setting Procedure
270
Examples of DTC Usage
271
Normal Transfer
271
Chain Transfer
271
Interrupt Handling
273
Chain Transfer When Counter = 0
273
Interrupt
275
Interrupt Sources
275
Event Link
275
Low Power Consumption Function
275
Usage Notes
276
Transfer Information Start Address
276
Event Link Controller (ELC)
277
Overview
277
Register Descriptions
278
ELCR : Event Link Controller Register
278
Elsegrn : Event Link Software Event Generation Register N (N = 0, 1)
278
Elsrn : Event Link Setting Register N (N = 0 to 3, 8, 9, 12, 14, 15, 18)
279
Event Link Controller (ELC)
280
Operation
283
Relation between Interrupt Handling and Event Linking
283
Linking Events
283
Example of Procedure for Linking Events
284
Usage Notes
284
Linking DTC Transfer End Signals as Events
284
Setting Clocks
284
Module-Stop Function Setting
284
ELC Delay Time
284
I/O Ports
286
Overview
286
Register Descriptions
288
PCNTR1/PODR/PDR : Port Control Register 1
288
PCNTR2/EIDR/PIDR : Port Control Register 2
289
PCNTR3/PORR/POSR : Port Control Register 3
290
PCNTR4/EORR/EOSR : Port Control Register 4
291
Pmnpfs/Pmnpfs_Ha/Pmnpfs_By : Port Mn Pin Function Select Register (M = 0 to 8, N = 00 to 15)
292
PWPR : Write-Protect Register
294
PRWCNTR : Port Read Wait Control Register
294
Operation
294
General I/O Ports
294
Port Function Select
295
Port Group Function for ELC
295
Wait Function for Port Read
297
Handling of Unused Pins
297
Usage Notes
298
Procedure for Specifying the Pin Functions
298
Procedure for Using Port Group Input
298
Port Output Data Register (PODR) Summary
298
Notes on Using Analog Functions
299
Peripheral Select Settings for each Product
299
Key Interrupt Function (KINT)
304
Overview
304
Register Descriptions
304
KRCTL : Key Return Control Register
304
KRF : Key Return Flag Register
305
KRM : Key Return Mode Register
305
Operation
305
Operation When Not Using the Key Interrupt Flags (KRCTL.KRMD = 0)
305
Operation When Using the Key Interrupt Flags (KRCTL.KRMD = 1)
306
Usage Notes
308
Port Output Enable for GPT (POEG)
309
Overview
309
Register Descriptions
310
Poeggn : POEG Group N Setting Register (N = A, B)
310
Output-Disable Control Operation
311
Pin Input Level Detection Operation
312
Digital Filter
312
Output-Disable Requests from the GPT
312
Output-Disable Control Using Detection of Stopped Oscillation
312
Output-Disable Control Using Registers
312
Release from Output-Disable
313
Interrupt Sources
313
External Trigger Output to the GPT
314
Usage Notes
314
Transition to Software Standby Mode
314
Specifying Pins Associated with the GPT
314
General PWM Timer (GPT)
315
Overview
315
Register Descriptions
318
GTWP : General PWM Timer Write-Protection Register
318
GTSTR : General PWM Timer Software Start Register
319
GTSTP : General PWM Timer Software Stop Register
319
GTCLR : General PWM Timer Software Clear Register
320
GTSSR : General PWM Timer Start Source Select Register
320
GTPSR : General PWM Timer Stop Source Select Register
323
GTCSR : General PWM Timer Clear Source Select Register
325
GTUPSR : General PWM Timer up Count Source Select Register
328
GTDNSR : General PWM Timer down Count Source Select Register
330
GTICASR : General PWM Timer Input Capture Source Select Register a
333
GTICBSR : General PWM Timer Input Capture Source Select Register B
335
GTCR : General PWM Timer Control Register
338
GTUDDTYC : General PWM Timer Count Direction and Duty Setting Register
340
GTIOR : General PWM Timer I/O Control Register
342
GTINTAD : General PWM Timer Interrupt Output Setting Register
346
GTST : General PWM Timer Status Register
347
GTBER : General PWM Timer Buffer Enable Register
351
GTCNT : General PWM Timer Counter
352
Gtccrn : General PWM Timer Compare Capture Register N (N = a to F)
352
GTPR : General PWM Timer Cycle Setting Register
353
GTPBR : General PWM Timer Cycle Setting Buffer Register
353
GTDTCR : General PWM Timer Dead Time Control Register
353
GTDVU : General PWM Timer Dead Time Value Register U
354
OPSCR : Output Phase Switching Control Register
355
Operation
357
Basic Operation
357
Counter Operation
357
Counter Clear Operation
361
Input Capture Function
364
Buffer Operation
365
PWM Output Operating Mode
372
Automatic Dead Time Setting Function
381
Count Direction Changing Function
385
Function of Output Duty 0% and 100
385
Hardware Count Start/Count Stop and Clear Operation
387
Synchronized Operation
392
PWM Output Operation Examples
396
Phase Counting Function
402
Output Phase Switching (GPT_OPS)
412
Interrupt Sources
419
DTC Activation
421
Operations Linked by ELC
421
Event Signal Output to ELC
421
Event Signal Inputs from ELC
421
Noise Filter Function
421
Protection Function
422
Write-Protection for Registers
422
Disabling of Buffer Operation
422
Gtiocnm Pin Output Negate Control (N = 0 to 9, M = A, B)
423
Initialization Method of Output Pins
424
Pin Settings after Reset
424
Pin Initialization Due to Error During Operation
425
Usage Notes
425
Module-Stop Function Setting
425
Gtccrn Settings During Compare Match Operation (N = a to F)
425
Setting Range for GTCNT Counter
426
Starting and Stopping the GTCNT Counter
426
Priority Order of each Event
427
Low Power Asynchronous General Purpose Timer (AGT)
428
Overview
428
Register Descriptions
430
AGT : AGT Counter Register
430
AGTCMA : AGT Compare Match a Register
430
AGTCMB : AGT Compare Match B Register
431
AGTCR : AGT Control Register
431
AGTMR1 : AGT Mode Register 1
433
AGTMR2 : AGT Mode Register 2
433
AGTIOC : AGT I/O Control Register
435
AGTISR : AGT Event Pin Select Register
436
AGTCMSR : AGT Compare Match Function Select Register
437
AGTIOSEL : AGT Pin Select Register
437
Operation
438
Reload Register and Counter Rewrite Operation
438
Reload Register and AGT Compare Match A/B Register Rewrite Operation
440
Timer Mode
441
Pulse Output Mode
442
Event Counter Mode
443
Pulse Width Measurement Mode
444
Pulse Period Measurement Mode
445
Compare Match Function
446
Output Settings for each Mode
447
Standby Mode
448
Interrupt Sources
449
Event Signal Output to ELC
449
Usage Notes
449
Count Operation Start and Stop Control
449
Access to Counter Register
450
When Changing Mode
450
Output Pin Setting
450
Digital Filter
450
How to Calculate Event Number, Pulse Width, and Pulse Period
451
When Count Is Forcibly Stopped by TSTOP Bit
451
When Selecting AGT0 Underflow as the Count Source
451
Module-Stop Function
451
Realtime Clock (RTC)
452
Overview
452
Register Descriptions
453
R64CNT : 64-Hz Counter
453
RSECCNT : Second Counter (in Calendar Count Mode)
454
RMINCNT : Minute Counter (in Calendar Count Mode)
454
RHRCNT : Hour Counter (in Calendar Count Mode)
455
RWKCNT : Day-Of-Week Counter (in Calendar Count Mode)
455
Bcntn : Binary Counter N (N = 0 to 3) (in Binary Count Mode)
456
RDAYCNT : Day Counter
456
RMONCNT : Month Counter
457
RYRCNT : Year Counter
457
RSECAR : Second Alarm Register (in Calendar Count Mode)
458
RMINAR : Minute Alarm Register (in Calendar Count Mode)
458
RHRAR : Hour Alarm Register (in Calendar Count Mode)
459
RWKAR : Day-Of-Week Alarm Register (in Calendar Count Mode)
460
Bcntnar : Binary Counter N Alarm Register (N = 0 to 3) (in Binary Count Mode)
461
RDAYAR : Date Alarm Register (in Calendar Count Mode)
461
RMONAR : Month Alarm Register (in Calendar Count Mode)
462
RYRAR : Year Alarm Register (in Calendar Count Mode)
462
RYRAREN : Year Alarm Enable Register (in Calendar Count Mode)
463
Bcntnaer : Binary Counter N Alarm Enable Register (N = 0, 1) (in Binary Count Mode)
463
BCNT2AER : Binary Counter 2 Alarm Enable Register (in Binary Count Mode)
464
BCNT3AER : Binary Counter 3 Alarm Enable Register (in Binary Count Mode)
464
RCR1 : RTC Control Register 1
465
RCR2 : RTC Control Register 2 (in Calendar Count Mode)
466
RCR2 : RTC Control Register 2 (in Binary Count Mode)
468
RCR4 : RTC Control Register 4
469
RFRL : Frequency Register L
470
RFRH : Frequency Register H
470
RADJ : Time Error Adjustment Register
471
Operation
471
Outline of Initial Settings of Registers after Power on
471
Operation Mode, Clock and Count Mode Setting Procedure
472
Setting the Time
473
30-Second Adjustment
474
Reading 64-Hz Counter and Time
475
Alarm Function
477
Using the Alarm Function
477
Procedure for Disabling Alarm Interrupt
478
Time Error Adjustment Function
478
Automatic Adjustment
478
Adjustment by Software
480
Register Settings
480
Interrupt Sources
481
Event Link Output
482
Interrupt Handling and Event Linking
482
Usage Notes
482
Register Writing During Counting
482
Use of Periodic Interrupts
483
RTCOUT (1-Hz/64-Hz) Clock Output
483
Transitions to Low Power Modes after Setting Registers
484
Notes on Writing to and Reading from Registers
484
Changing the Count Mode
484
Initialization Procedure When the RTC Is Not to be Used
484
Watchdog Timer (WDT)
486
Overview
486
Register Descriptions
487
WDTRR : WDT Refresh Register
487
WDTCR : WDT Control Register
488
WDTSR : WDT Status Register
490
WDTRCR : WDT Reset Control Register
491
WDTCSTPR : WDT Count Stop Control Register
492
Option Function Select Register 0 (OFS0)
492
Operation
492
Count Operation in each Start Mode
492
Register Start Mode
493
Auto Start Mode
494
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
495
Refresh Operation
496
Status Flags
497
Reset Output
497
Interrupt Sources
497
Reading the Down-Counter Value
498
Association between Option Function Select Register 0 (OFS0) and WDT Registers
498
Output to the Event Link Controller (ELC)
499
Usage Notes
499
ICU Event Link Setting Register N (Ielsrn) Setting
499
Independent Watchdog Timer (IWDT)
500
Overview
500
Register Descriptions
501
IWDTRR : IWDT Refresh Register
501
IWDTSR : IWDT Status Register
502
OFS0 : Option Function Select Register 0
503
Operation
505
Auto Start Mode
505
Refresh Operation
506
Status Flags
507
Reset Output
508
Interrupt Sources
508
Reading the Down-Counter Value
508
Output to the Event Link Controller (ELC)
508
Usage Notes
509
Refresh Operations
509
Clock Division Ratio Setting
509
Constraints on the ICU Event Link Setting Register N (Ielsrn) Setting
509
Serial Communications Interface (SCI)
510
Overview
510
Register Descriptions
512
RSR : Receive Shift Register
512
RDR : Receive Data Register
513
RDRHL : Receive Data Register
513
FRDRHL/FRDRH/FRDRL : Receive FIFO Data Register
513
TDR : Transmit Data Register
515
TDRHL : Transmit Data Register
515
FTDRHL/FTDRH/FTDRL : Transmit FIFO Data Register
516
TSR : Transmit Shift Register
516
SMR : Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
517
SMR_SMCI : Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)
518
SCR : Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
519
SCR_SMCI : Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)
521
SSR : Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0)
523
SSR_FIFO : Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1)
525
SSR_SMCI : Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)
528
SCMR : Smart Card Mode Register
530
BRR : Bit Rate Register
531
MDDR : Modulation Duty Register
538
SEMR : Serial Extended Mode Register
540
SNFR : Noise Filter Setting Register
541
SIMR1 : IIC Mode Register 1
542
SIMR2 : IIC Mode Register 2
543
SIMR3 : IIC Mode Register 3
543
SISR : IIC Status Register
545
SPMR : SPI Mode Register
546
FCR : FIFO Control Register
547
FDR : FIFO Data Count Register
548
LSR : Line Status Register
549
CDR : Compare Match Data Register
550
DCCR : Data Compare Match Control Register
550
SPTR : Serial Port Register
552
Operation in Asynchronous Mode
552
Serial Data Transfer Format
553
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
554
Clock
555
Double-Speed Operation and Frequency of 6 Times the Bit Rate
555
CTS and RTS Functions
556
Address Match (Receive Data Match Detection) Function
556
SCI Initialization in Asynchronous Mode
558
Serial Data Transmission in Asynchronous Mode
560
Serial Data Reception in Asynchronous Mode
565
Multi-Processor Communication Function
578
Multi-Processor Serial Data Transmission
580
Multi-Processor Serial Data Reception
583
Operation in Clock Synchronous Mode
588
Clock
589
CTS and RTS Functions
589
SCI Initialization in Clock Synchronous Mode
590
Serial Data Transmission in Clock Synchronous Mode
591
Serial Data Reception in Clock Synchronous Mode
595
Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode
600
Operation in Smart Card Interface Mode
603
Example Connection
603
Data Format (Except in Block Transfer Mode)
603
Block Transfer Mode
605
Receive Data Sampling Timing and Reception Margin
605
SCI Initialization (Smart Card Interface Mode)
606
Serial Data Transmission (Except in Block Transfer Mode)
607
Serial Data Reception (Except in Block Transfer Mode)
609
Clock Output Control
611
Operation in Simple IIC Mode
612
Generation of Start, Restart, and Stop Conditions
613
Clock Synchronization
614
Sdan Output Delay
615
SCI Initialization in Simple IIC Mode
615
Operation in Master Transmission in Simple IIC Mode
616
Master Reception in Simple IIC Mode
619
Operation in Simple SPI Mode
621
States of Pins in Master and Slave Modes
621
SS Function in Master Mode
622
SS Function in Slave Mode
622
Relationship between Clock and Transmit/Receive Data
622
SCI Initialization in Simple SPI Mode
623
Transmission and Reception of Serial Data in Simple SPI Mode
623
Bit Rate Modulation Function
623
Interrupt Sources
624
Buffer Operation for Scin_Txi and Scin_Rxi Interrupts (Non-FIFO Selected)
624
Buffer Operation for Scin_Txi and Scin_Rxi Interrupts (FIFO Selected)
624
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes
624
Interrupts in Smart Card Interface Mode
626
Interrupts in Simple IIC Mode
627
Event Linking
627
Address Non-Match Event Output (SCI0_DCUF)
628
Noise Cancellation Function
628
Usage Notes
629
Settings for the Module-Stop Function
629
SCI Operation During Low Power State
629
Break Detection and Processing
634
Mark State and Production of Breaks
635
Receive Error Flags and Transmit Operation in Clock Synchronous Mode and Simple SPI Mode
635
Restrictions on Clock Synchronous Transmission in Clock Synchronous Mode and Simple SPI Mode
635
Continuous Transmission
635
Restrictions on Using DTC
636
Notes on Starting Transfer
637
External Clock Input in Clock Synchronous Mode and Simple SPI Mode
637
Limitations on Simple SPI Mode
637
Slave Mode
638
Notes on Transmitt Enable Bit (SCR.TE)
638
Note on Stopping Reception When Using the RTS Function in Asynchronous Mode
638
I2C Bus Interface (IIC)
639
Overview
639
Register Descriptions
641
Iccr1 : I
641
Iccr2 : I
643
Icmr1 : I
646
Icmr2 : I
647
Icmr3 : I
648
ICFER : I C Bus Function Enable Register
650
Icser : I
651
Icier : I
652
Icsr1 : I
654
Icsr2 : I
656
Bus Status Register 2
656
Icwur : I
659
Bus Wakeup Unit Register
659
Icwur2 : I
660
Bus Wakeup Unit Register 2
660
Sarly : Slave Address Register Ly (y = 0 to 2)
661
Saruy : Slave Address Register Uy (y = 0 to 2)
662
Icbrl : I
662
Bus Bit Rate Low-Level Register
662
ICBRH : I C Bus Bit Rate High-Level Register
663
Icdrt : I
664
Icdrr : I
664
Icdrs : I
665
Operation
665
Communication Data Format
665
Initial Settings
666
Master Transmit Operation
667
Master Receive Operation
671
Slave Transmit Operation
676
Slave Receive Operation
678
SCL Synchronization Circuit
680
SDA Output Delay Function
681
Digital Noise Filter Circuits
682
Address Match Detection
683
Slave-Address Match Detection
683
Detection of General Call Address
686
Device-ID Address Detection
687
Host Address Detection
688
Wakeup Function
689
Normal Wakeup Mode 1
690
Normal Wakeup Mode 2
693
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes)
695
Automatic Low-Hold Function for SCL
698
Function to Prevent Wrong Transmission of Transmit Data
698
NACK Reception Transfer Suspension Function
699
Function to Prevent Failure to Receive Data
700
Arbitration-Lost Detection Functions
701
Master Arbitration-Lost Detection (MALE Bit)
701
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
703
Slave Arbitration-Lost Detection (SALE Bit)
704
Start, Restart, and Stop Condition Issuing Function
705
Issuing a Start Condition
705
Issuing a Restart Condition
705
Issuing a Stop Condition
707
Bus Hanging
707
Timeout Function
707
Extra SCL Clock Cycle Output Function
708
IIC Reset and Internal Reset
709
Smbus Operation
709
Smbus Timeout Measurement
710
Packet Error Code (PEC)
711
Smbus Host Notification Protocol (Notify ARP Master Command)
711
Interrupt Sources
711
Buffer Operation for Iicn_Txi and Iicn_Rxi Interrupts
712
State of Registers When Issuing each Condition
712
Event Link Output
713
Interrupt Handling and Event Linking
713
Usage Notes
714
Settings for the Module-Stop Function
714
Notes on Starting Transfer
714
Controller Area Network (CAN) Module
715
Overview
715
Register Descriptions
717
CTLR : Control Register
717
BCR : Bit Configuration Register
720
Mkr[K] : Mask Register K (K = 0 to 7)
721
Fidcrk : FIFO Received ID Compare Register K (K = 0, 1)
722
MKIVLR : Mask Invalid Register
723
Mailbox Registers
723
MIER : Mailbox Interrupt Enable Register
727
MIER_FIFO : Mailbox Interrupt Enable Register for FIFO Mailbox Mode
727
Mctl_Tx[J] : Message Control Register for Transmit (J = 0 to 31)
728
Mctl_Rx[J] : Message Control Register for Receive (J = 0 to 31)
730
RFCR : Receive FIFO Control Register
732
RFPCR : Receive FIFO Pointer Control Register
734
TFCR : Transmit FIFO Control Register
735
TFPCR : Transmit FIFO Pointer Control Register
736
STR : Status Register
737
MSMR : Mailbox Search Mode Register
739
MSSR : Mailbox Search Status Register
739
CSSR : Channel Search Support Register
740
AFSR : Acceptance Filter Support Register
741
EIER : Error Interrupt Enable Register
742
EIFR : Error Interrupt Factor Judge Register
743
RECR : Receive Error Count Register
745
TECR : Transmit Error Count Register
746
ECSR : Error Code Store Register
746
TSR : Time Stamp Register
747
TCR : Test Control Register
748
Listen-Only Mode
748
Operation Modes
749
CAN Reset Mode
750
CAN Halt Mode
751
CAN Sleep Mode
752
CAN Operation Mode (Excluding Bus-Off State)
752
CAN Operation Mode (Bus-Off State)
753
Data Transfer Rate Configuration
753
Clock Setting
753
Bit Timing Setting
753
Data Transfer Rate
754
Mailbox and Mask Register Structure
754
Acceptance Filtering and Masking Functions
756
Reception and Transmission
758
Reception
758
Transmission
760
Interrupts
761
Usage Notes
762
Settings for the Module-Stop State
762
Settings for the Operating Clock
762
Serial Peripheral Interface (SPI)
763
Overview
763
SPI Block Diagram
764
Register Descriptions
765
SPCR : SPI Control Register
765
SSLP : SPI Slave Select Polarity Register
767
SPPCR : SPI Pin Control Register
767
SPSR : SPI Status Register
768
Multi-Master Mode
769
SPDR/SPDR_HA : SPI Data Register
770
Bus Interface
771
SPBR : SPI Bit Rate Register
772
SPDCR : SPI Data Control Register
773
SPCKD : SPI Clock Delay Register
774
SSLND : SPI Slave Select Negation Delay Register
774
SPND : SPI Next-Access Delay Register
775
SPCR2 : SPI Control Register 2
775
SPCMD0 : SPI Command Register 0
777
Operation
778
Overview of SPI Operation
779
Controlling the SPI Pins
780
SPI System Configuration Examples
781
Data Formats
786
Serial Peripheral Interface (SPI)
788
Transfer Formats
795
Data Transfer Modes
797
Transmit Buffer Empty and Receive Buffer Full Interrupts
798
Error Detection
800
Parity Errors
803
Initializing the SPI
805
SPI Operation
805
Initialization Flow
807
Slave Mode Operation
811
Burst Transfer
812
Clock Synchronous Operation
816
Master Mode Operation
816
Loopback Mode
820
Self-Diagnosis of Parity Bit Function
820
Interrupt Sources
821
Event Link Controller Event Output
822
Receive Buffer Full Event Output
822
Transmit Buffer Empty Event Output
823
Mode-Fault, Underrun, Overrun, or Parity Error Event Output
823
SPI Idle Event Output
823
Transmission-Completed Event Output
823
Usage Notes
824
Settings for the Module-Stop State
824
Constraint on Low-Power Functions
824
Constraints on Starting Transfer
824
Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output
824
Constraints on the SPSR.SPRF and SPSR.SPTEF Flags
824
Cyclic Redundancy Check (CRC) Calculator
825
Overview
825
Register Descriptions
826
CRCCR0 : CRC Control Register 0
826
CRCCR1 : CRC Control Register 1
827
CRCDIR/CRCDIR_BY : CRC Data Input Register
827
CRCDOR/CRCDOR_HA/CRCDOR_BY : CRC Data Output Register
828
CRCSAR : Snoop Address Register
828
Operation
828
Basic Operation
828
CRC Snoop Function
832
Usage Notes
833
Settings for the Module-Stop State
833
Note on Transmission
833
Bit A/D Converter (ADC12)
834
Overview
834
Register Descriptions
838
Addrn : A/D Data Registers N
838
ADDBLDR : A/D Data Duplexing Register
839
Addbldrn : A/D Data Duplexing Register N (N = A, B)
840
ADTSDR : A/D Temperature Sensor Data Register
841
ADOCDR : A/D Internal Reference Voltage Data Register
843
ADCTDR : A/D CTSU TSCAP Voltage Data Register
844
ADRD : A/D Self-Diagnosis Data Register
845
ADCSR : A/D Control Register
846
ADANSA0 : A/D Channel Select Register A0
850
ADANSA1 : A/D Channel Select Register A1
851
ADANSB0 : A/D Channel Select Register B0
851
ADANSB1 : A/D Channel Select Register B1
852
ADADS0 : A/D-Converted Value Addition/Average Channel Select Register 0
852
ADADS1 : A/D-Converted Value Addition/Average Channel Select Register 1
853
ADADC : A/D-Converted Value Addition/Average Count Select Register
854
ADCER : A/D Control Extended Register
855
ADSTRGR : A/D Conversion Start Trigger Select Register
856
ADEXICR : A/D Conversion Extended Input Control Registers
858
Adsstrn/Adsstrl/Adsstrt/Adsstro : A/D Sampling State Register
859
ADDISCR : A/D Disconnection Detection Control Register
860
ADACSR : A/D Conversion Operation Mode Select Register
861
ADGSPCR : A/D Group Scan Priority Control Register
861
ADCMPCR : A/D Compare Function Control Register
862
ADCMPANSR0 : A/D Compare Function Window a Channel Select Register 0
864
ADCMPANSR1 : A/D Compare Function Window a Channel Select Register 1
864
ADCMPANSER : A/D Compare Function Window a Extended Input Select Register
865
ADCMPLR0 : A/D Compare Function Window a Comparison Condition Setting Register
865
ADCMPLR1 : A/D Compare Function Window a Comparison Condition Setting Register
866
ADCMPLER : A/D Compare Function Window a Extended Input Comparison Condition Setting Register
867
Adcmpdrn : A/D Compare Function Window a Lower-Side/Upper-Side Level Setting Register (N = 0, 1)
868
Adwinnlb : A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register (N = L, U)
869
ADCMPSR0 : A/D Compare Function Window a Channel Status Register 0
871
ADCMPSR1 : A/D Compare Function Window a Channel Status Register1
871
ADCMPSER : A/D Compare Function Window a Extended Input Channel Status Register
872
ADCMPBNSR : A/D Compare Function Window B Channel Select Register
873
ADCMPBSR : A/D Compare Function Window B Status Register
874
ADWINMON : A/D Compare Function Window A/B Status Monitor Register
875
ADHVREFCNT : A/D High-Potential/Low-Potential Reference Voltage Control Register
876
Operation
877
Scanning Operation
877
Single Scan Mode
878
Continuous Scan Mode
882
Group Scan Mode
884
Compare Function for Windows a and B
893
Analog Input Sampling and Scan Conversion Time
897
Usage Example of A/D Data Register Automatic Clearing Function
899
A/D-Converted Value Addition/Average Mode
900
Disconnection Detection Assist Function
900
Starting A/D Conversion with an Asynchronous Trigger
902
Starting A/D Conversion with a Synchronous Trigger from a Peripheral Module
903
Interrupt Sources and DTC Transfer Requests
903
Interrupt Requests
903
Event Link Function
904
Event Output to the ELC
904
ADC12 Operation through an Event from the ELC
904
Selecting Reference Voltage
905
A/D Conversion Procedure When Selecting Internal Reference Voltage as High-Potential Reference Voltage
905
Usage Notes
905
Constraints on Setting the Registers
905
Constraints on Reading the Data Registers
905
Constraints on Stopping A/D Conversion
906
A/D Conversion Restart and Termination Timing
908
Constraints on Scan End Interrupt Handling
908
Settings for the Module-Stop Function
908
Notes on Entering the Low-Power States
908
Error in Absolute Accuracy When Disconnection Detection Assistance Is in Use
908
ADHSC Bit Rewriting Procedure
908
Constraints on Operating Modes and Status Bits
909
Notes on Board Design
909
Constraints on Noise Prevention
909
Port Settings When Using the ADC12 Input
910
Notes on Canceling Software Standby Mode
910
Bit D/A Converter (DAC12)
911
Overview
911
Register Descriptions
912
DADR0 : D/A Data Register 0
912
DACR : D/A Control Register
912
DADPR : DADR0 Format Select Register
913
DAADSCR : D/A A/D Synchronous Start Control Register
913
DAVREFCR : D/A VREF Control Register
914
Operation
914
Reducing Interference between D/A and A/D Conversion
915
Event Link Operation Setting Procedure
917
DA0 Event Link Operation Setting Procedure
917
Usage Notes on Event Link Operation
917
Usage Notes
917
Settings for the Module-Stop Function
917
DAC12 Operation in the Module-Stop State
917
DAC12 Operation in Software Standby Mode
917
Constraint on Usage When Interference Reduction between D/A and A/D Conversion Is Enabled
917
Temperature Sensor (TSN)
918
Overview
918
Register Descriptions
918
TSCDR : Temperature Sensor Calibration Data Register
918
Using the Temperature Sensor
919
Preparation for Using the Temperature Sensor
919
Procedures for Using the Temperature Sensor
920
Low Power Analog Comparator (ACMPLP)
921
Overview
921
Register Descriptions
923
COMPMDR : ACMPLP Mode Setting Register
923
COMPFIR : ACMPLP Filter Control Register
924
COMPOCR : ACMPLP Output Control Register
924
Operation
925
Noise Filter
927
ACMPLP Interrupts
928
ELC Event Output
929
Interrupt Handling and ELC Linking
929
Comparator Pin Output
929
Usage Notes
929
Module-Stop Function Settings
929
Capacitive Sensing Unit 2 (CTSU)
930
Overview
930
Register Descriptions
932
CTSUCRA/CTSUCRAH/CTSUCRAL/CTSUCR3/CTSUCR2/CTSUCR1/CTSUCR0 : CTSU Control Register a
932
CTSUCRB/CTSUCRBH/CTSUCRBL/CTSUDCLKC/CTSUSST/CTSUSDPRS : CTSU Control Register B
937
CTSUMCH/CTSUMCHH/CTSUMCHL/CTSUMFAF/CTSUMCH1/CTSUMCH0 : CTSU Measurement Channel Register
939
CTSUCHACA/CTSUCHACAH/CTSUCHACAL/CTSUCHAC3/CTSUCHAC2/CTSUCHAC1/ CTSUCHAC0 : CTSU Channel Enable Control Register a
941
CTSUCHACB/CTSUCHACBL/CTSUCHAC4 : CTSU Channel Enable Control Register B
942
CTSUCHTRCA/CTSUCHTRCAH/CTSUCHTRCAL/CTSUCHTRC3/CTSUCHTRC2/ CTSUCHTRC1/CTSUCHTRC0 : CTSU Channel Transmit/Receive Control Register a
943
CTSUCHTRCB/CTSUCHTRCBL/CTSUCHTRC4 : CTSU Channel Transmit/Receive Control Register B
944
CTSUSR/CTSUSRH/CTSUSRL/CTSUSR2/CTSUST/CTSUSR0 : CTSU Status Register
945
CTSUSO/CTSUSO1/CTSUSO0 : CTSU Sensor Offset Register
948
CTSUSCNT/CTSUSC : CTSU Sensor Counter Register
949
CTSUCALIB/CTSUDBGR1/CTSUDBGR0 : CTSU Calibration Register
950
CTSUSUCLKA/CTSUSUCLK1/CTSUSUCLK0 : CTSU Sensor Unit Clock Control Register a
953
CTSUSUCLKB/CTSUSUCLK3/CTSUSUCLK2 : CTSU Sensor Unit Clock Control Register B
954
CTSUCFCCNT/CTSUCFCCNTL : CTSU CFC Counter Register
955
CTSUTRIMA : CTSU Trimming Register a
955
CTSUTRIMB : CTSU Trimming Register B
956
Data Operation Circuit (DOC)
957
Overview
957
DOC Register Descriptions
957
DOCR : DOC Control Register
957
DODIR : DOC Data Input Register
958
DODSR : DOC Data Setting Register
959
Operation
959
Data Comparison Mode
959
Data Addition Mode
959
Data Subtraction Mode
960
Interrupt Source
960
Output of an Event Signal to the Event Link Controller (ELC)
961
Usage Notes
961
Settings for the Module-Stop State
961
Sram
962
Overview
962
Register Descriptions
962
PARIOAD : SRAM Parity Error Operation after Detection Register
962
SRAMPRCR : SRAM Protection Register
963
ECCMODE : ECC Operating Mode Control Register
963
ECC2STS : ECC 2-Bit Error Status Register
964
ECC1STSEN : ECC 1-Bit Error Information Update Enable Register
964
ECC1STS : ECC 1-Bit Error Status Register
965
ECCPRCR : ECC Protection Register
965
ECCPRCR2 : ECC Protection Register 2
966
ECCETST : ECC Test Control Register
966
ECCOAD : SRAM ECC Error Operation after Detection Register
967
Trace Control (for the MTB)
967
Coresight (for MTB)
967
Operation
968
ECC Function
968
ECC Error Generation
968
ECC Decoder Testing
969
Parity Calculation Function
970
SRAM Error Sources
971
Access Cycle
972
Low-Power Function
972
Usage Notes
972
Instruction Fetch from the SRAM Area
972
SRAM Store Buffer
972
Flash Memory
973
Overview
973
Memory Structure
974
Register Descriptions
975
DFLCTL : Data Flash Control Register
975
PFBER : Prefetch Buffer Enable Register
976
FENTRYR : Flash P/E Mode Entry Register
976
FPR : Protection Unlock Register
977
FPSR : Protection Unlock Status Register
977
FPMCR : Flash P/E Mode Control Register
978
FISR : Flash Initial Setting Register
979
FRESETR : Flash Reset Register
980
FASR : Flash Area Select Register
980
FCR : Flash Control Register
981
FEXCR : Flash Extra Area Control Register
982
FSARH : Flash Processing Start Address Register H
985
FSARL : Flash Processing Start Address Register L
985
FEARH : Flash Processing End Address Register H
985
FEARL : Flash Processing End Address Register L
986
FWBL0 : Flash Write Buffer Register L0
986
FWBH0 : Flash Write Buffer Register H0
987
FRBL0 : Flash Read Buffer Register L0
987
FRBH0 : Flash Read Buffer Register H0
987
FSTATR00 : Flash Status Register 0
988
FSTATR2 : Flash Status Register 2
989
FSTATR1 : Flash Status Register 1
990
FEAMH : Flash Error Address Monitor Register H
990
FEAML : Flash Error Address Monitor Register L
991
FSCMR : Flash Start-Up Setting Monitor Register
991
FAWSMR : Flash Access Window Start Address Monitor Register
991
FAWEMR : Flash Access Window End Address Monitor Register
992
Instruction Prefetch from Flash Memory
992
Operating Modes Associated with the Flash Memory
992
ID Code Protection
993
Overview of Functions
994
Security Functions
995
Configuration Area Bit Map
996
Startup Area Select
996
Protection by Access Window
997
Programming Commands
998
Suspend Operation
998
Protection
998
Startup Program Protection
998
Area Protection
999
Serial Programming Mode
1000
SCI Boot Mode
1000
Using a Serial Programmer
1001
Serial Programming
1001
Self-Programming
1001
Overview
1001
Background Operation
1002
Programming and Erasure
1002
Sequencer Modes
1002
Read Mode
1003
Software Commands
1003
Software Command Usage
1004
Reading the Flash Memory
1020
Reading the Code Flash Memory
1020
Reading the Data Flash Memory
1020
Usage Notes
1020
Erase Suspended Area
1020
Suspension by Erase Suspend Commands
1021
Constraints on Additional Writes
1021
Reset During Programming and Erasure
1021
Non-Maskable Interrupt Disabled During Programming and Erasure
1021
Location of Interrupt Vectors During Programming and Erasure
1021
Programming and Erasure in Subosc-Speed Operating Mode
1021
Abnormal Termination During Programming and Erasure
1021
Actions Prohibited During Programming and Erasure
1021
Additional Programming Disabled
1021
Flash if Clock (ICLK) During Program/Erase
1022
AES Engine
1023
True Random Number Generator (TRNG)
1024
Internal Voltage Regulator
1025
Overview
1025
Operation
1025
Usage Notes
1026
Electrical Characteristics
1027
Absolute Maximum Ratings
1027
DC Characteristics
1028
Tj/Ta Definition
1028
I/O Vih, Vil
1029
I/O Ioh, Iol
1029
I/O VOH, VOL, and Other Characteristics
1035
Operating and Standby Current
1036
VCC Rise and Fall Gradient and Ripple Frequency
1039
AC Characteristics
1039
Frequency
1040
Clock Timing
1041
Reset Timing
1043
Wakeup Time
1044
NMI and IRQ Noise Filter
1047
I/O Ports, POEG, GPT, AGT, KINT, and ADC12 Trigger Timing
1048
CAC Timing
1050
SCI Timing
1051
SPI Timing
1058
IIC Timing
1064
CLKOUT Timing
1066
ADC12 Characteristics
1067
Absolute Accuracy
1074
DAC12 Characteristics
1075
TSN Characteristics
1076
OSC Stop Detect Characteristics
1077
POR and LVD Characteristics
1077
CTSU Characteristics
1082
Comparator Characteristics
1082
Flash Memory Characteristics
1083
Code Flash Memory Characteristics
1083
Data Flash Memory Characteristics
1085
Serial Wire Debug (SWD)
1087
DCDC Characteristics
1088
Appendix 1. Port States in each Processing Mode
1089
Appendix 2. Package Dimensions
1094
Appendix 3. I/O Registers
1097
Peripheral Base Addresses
1097
Access Cycles
1098
Register Descriptions
1100
Revision History
1115
Publication Date
1116

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