Rohm LAPIS ML620Q152A Manuals

Manuals and User Guides for Rohm LAPIS ML620Q152A. We have 1 Rohm LAPIS ML620Q152A manual available for free PDF download: User Manual

Rohm LAPIS ML620Q152A User Manual (556 pages)

16-bit Microcontroller

Brand: Rohm | Category: Microcontrollers | Size: 4 MB

Table of Contents
5
Overview
17
Features
18
Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)
21
Configuration of Functional Blocks
21
Block Diagram of ML620Q154A/ML620Q155A/ML620Q156A(TQFP52)
22
Block Diagram of ML620Q157A/ML620Q158A/ML620Q159A(QFP64)
23
Pin Layout
24
Pins
24
List of Pins
27
Pin Description
31
Handling of Unused Pins
34
CPU and Memory Space
35
Genral Description
36
Program Memory Space
36
Data Memory Space
39
Data Type
42
Instruction Length
42
Description of Registers
43
List of Registers
43
Data Segment Register (DSR)
44
Reset Function
45
Configuration
46
Description of Registers
46
Features
46
General Description
46
List of Pin
46
List of Registers
46
Reset Status Register (RSTAT)
47
Description of Operation
48
Operation of System Reset Mode
48
MCU Control Function
49
Configuration
50
Features
50
General Description
50
Description of Registers
51
List of Registers
51
Stop Code Acceptor (STPACP)
52
Standby Control Register (SBYCON)
53
Block Control Register 0 (BLKCON0)
54
Block Control Register 2 (BLKCON2)
55
Block Control Register 3 (BLKCON3)
56
Block Control Register 4 (BLKCON4)
57
Block Control Register 6 (BLKCON6)
58
Block Control Register 7 (BLKCON7)
59
Description of Operation
60
HALT Mode
60
Program Run Mode
60
STOP Mode
61
STOP Mode When the CPU Runs with Low-Speed Clock
61
STOP Mode When the CPU Runs with High-Speed Clock
62
Note on Return Operation from STOP/HALT Mode
63
Block Control Function
64
Interrupts (Ints)
65
Features
66
Description of Registers
67
List of Registers
67
Interrupt Enable Register 0 (IE0)
68
Interrupt Enable Register 1 (IE1)
69
Interrupt Enable Register 2 (IE2)
71
Interrupt Enable Register 3 (IE3)
72
Interrupt Enable Register 4 (IE4)
73
Interrupt Enable Register 5 (IE5)
74
Interrupt Enable Register 6 (IE6)
75
Interrupt Enable Register 7 (IE7)
77
Interrupt Request Register 0 (IRQ0)
78
Interrupt Request Register 1 (IRQ1)
79
Interrupt Request Register 2 (IRQ2)
81
Interrupt Request Register 3 (IRQ3)
82
Interrupt Request Register 4 (IRQ4)
84
Interrupt Request Register 5 (IRQ5)
85
Interrupt Request Register 6 (IRQ6)
86
Interrupt Request Register 7 (IRQ7)
88
Interrupt Level Control Enable Register (ILENL)
89
Current Interrupt Request Level Register (CILL)
90
Interrupt Level Control Register 01 (ILC01)
91
Interrupt Level Control Register 10 (ILC10)
92
Interrupt Level Control Register 11 (ILC11)
93
Interrupt Level Control Register 20 (ILC20)
94
Interrupt Level Control Register 21 (ILC21)
95
Interrupt Level Control Register 30 (ILC30)
96
Interrupt Level Control Register 31 (ILC31)
97
Interrupt Level Control Register 40 (ILC40)
98
Interrupt Level Control Register 51 (ILC51)
99
Interrupt Level Control Register 60 (ILC60)
100
Interrupt Level Control Register 61 (ILC61)
101
Interrupt Level Control Register 70 (ILC70)
102
Description of Operation
103
Maskable Interrupt Processing
104
Non-Maskable Interrupt Processing
104
Software Interrupt Processing
104
Notes on Interrupt Routine (When Interrupt Level Control Disabled)
105
Interrupt Processing When Interrupt Level Control Enabled
108
Flow Chart When Interrupt Level Control Enabled
109
How to Write Interrupt Processing When Interrupt Level Control Enabled
111
Interrupt Disable State
113
Clock Generation Circuit
114
Configuration
115
Features
115
General Description
115
Clock Configuration Diagram
117
List of Pins
117
Frequency Control Register 0(FCON0)
119
Frequency Control Register 1 (FCON1)
121
Frequency Control Register 3(FCON3)
122
Frequency Status Register (FSTAT)
124
Description of Operation
125
Low-Speed Built-In RC Oscillation Circuit
125
Low-Speed Clock
125
Low-Speed Crystal Oscillation Circuit
125
Operation of Low-Speed Clock Generation Circuit
126
High-Speed Built-In RC Oscillation Circuit
127
High-Speed Clock
127
PLL Oscillation Circuit
127
Operation of High-Speed Clock
128
Switching of System Clock
130
Functioning P21(OUTCLK) as the High-Speed Clock Output
131
Specifying Port Registers
131
Functioning P20 (LSCLK) as the Low-Speed Clock Output
132
Functioning P36 (LSCLK) as the Low-Speed Clock Output
133
Time Base Counter
134
Configuration
135
Features
135
Description of Registers
136
List of Registers
136
Low-Speed Time Base Counter (LTBR)
137
Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ)
138
Low-Speed Time Base Counter Interrupt Select Registers (LTBINT)
140
Description of Operation
141
Low-Speed Time Base Counter
141
8Bit Timer
143
Configuration
144
Features
144
Description of Registers
145
List of Registers
145
Timer N Data Register (TM0D)
146
Timer N Data Register (TM1D)
147
Timer 0 Counter Register (TM0C)
148
Timer 1 Counter Register (TM1C)
149
Timer 0 Control Register
150
Timer 1 Control Register
151
Timer Start Register 0 (TMSTR0)
152
Timer Stop Register 0 (TMSTP0)
153
Timer Status Register 0 (TMSTAT0)
154
Description of Operation
155
16Bit Timer
157
Configuration
158
Features
158
Description of Registers
159
List of Registers
159
16Bit Timer 8 Data Register L,H (TMH8DL,H)
160
16Bit Timer 9 Data Register L,H (TMH9DL,H)
161
16Bit Timer a Data Register L,H (TMHADL,H)
162
16Bit Timer B Data Register L,H (TMHBDL,H)
163
16Bit Timer 8 Counter Register L,H (TMH8CL,H)
164
16Bit Timer 9 Counter Register L,H (TMH9CL,H)
165
16Bit Timer a Counter Register L,H (TMHACL,H)
166
16Bit Timer B Counter Register L,H (TMHBCL,H)
167
16Bit Timer 8 Control Register L,H (TMH8CON)
168
16Bit Timer a Control Register L,H (TMHACON)
170
16Bit Timer B Control Register L,H (TMHBCON)
171
16Bit Timer Start Register 0 (TMHSTR0)
172
16Bit Timer Stop Register 0 (TMHSTP0)
173
16Bit Timer Status Register 0 (TMHSTAT0)
174
Description of Operation
175
Watchdog Timer
177
Configuration
178
Features
178
General Description
178
Description of Registers
179
List of Registers
179
Watchdog Timer Control Register (WDTCON)
180
Watchdog Timer Mode Register (WDTMOD)
181
Description of Operation
182
Pwm
185
Features
186
General Description
186
Configuration
187
List of Pins
191
Description of Registers
192
List of Registers
192
PWM4 Period Registers (PW4PL, PW4PH)
194
PWM4 Duty Registers (PW4DL, PW4DH)
195
PWM4 Counter Registers (PW4CL, PW4CH)
196
PWM4 Control Register 0 (PW4CON0)
197
PWM4 Control Register 1 (PW4CON1)
199
PWM4 Control Register 2 (PW4CON2)
200
PWM4 Control Register 3 (PW4CON3)
202
PWM4 Control Register 4 (PW4CON4)
203
PWM4 Control Register 5 (PW4CON5)
204
PWM4 Control Register 6 (PW4CON6)
205
PWM5 Period Registers (PW5PL, PW5PH)
206
PWM5 Duty Registers (PW5DL, PW5DH)
207
PWM5 Counter Registers (PW5CL, PW5CH)
208
PWM5 Control Register 0 (PW5CON0)
209
PWM5 Control Register 1 (PW5CON1)
211
PWM5 Control Register 2 (PW5CON2)
212
PWM5 Control Register 4 (PW5CON4)
214
PWM5 Control Register 5 (PW5CON5)
215
PWM5 Control Register 6 (PW5CON6)
216
PWM6 Period Registers (PW6PL, PW6PH)
217
PWM6 Duty Registers (PW6DL, PW6DH)
218
PWM6 Counter Registers (PW6CL, PW6CH)
219
PWM6 Control Register 0 (PW6CON0)
220
PWM6 Control Register 1 (PW6CON1)
222
PWM6 Control Register 2 (PW6CON2)
223
PWM6 Control Register 3 (PW6CON3)
225
PWM6 Control Register 4 (PW6CON4)
226
PWM6 Control Register 5 (PW6CON5)
227
PWM6 Control Register 6 (PW6CON6)
228
PWM7 Period Registers (PW7PL, PW7PH)
229
PWM7 Duty Registers (PW7DL, PW7DH)
230
PWM7 Counter Registers (PW7CL, PW7CH)
231
PWM7 Control Register 0 (PW7CON0)
232
PWM7 Control Register 1 (PW7CON1)
234
PWM7 Control Register 2 (PW7CON2)
235
PWM7 Control Register 4 (PW7CON4)
237
PWM7 Control Register 5 (PW7CON5)
238
PWM7 Control Register 6 (PW7CON6)
239
Description of Operation
240
PWM4 and PWM5, Single Mode / Repeat Mode (P45MD="0", Pnmd="0")
244
PWM4 and PWM5, Single Mode / One Shot Mode (P45MD="0", Pnmd="1")
246
PWM4 and PWM5, Coupled Mode (with no Dead-Time Specified) / Repeat Mode (P45MD="1", P4DTMD="0", P4MD="0")
248
PWM4 and PWM5, Coupled Mode (with no Dead-Time Specified) / One Shot Mode (P45MD="1", P4DTMD="0", P4MD="1")
250
PWM4 and PWM5, Coupled Mode (with Dead-Time Specified) / Repeat Mode (P45MD="1", P4DTMD="1", P4MD="0")
252
PWM4 and PWM5, Coupled Mode (with Dead-Time Specified) / One Shot Mode (P45MD="1", P4DTMD="1", P4MD="1")
255
PWM4/PWM5 Start/Stop/Clear Operation by the External Control
258
Software Start Mode
259
External Input Start Mode
261
Software Start or External Input Clear Mode
263
Emergency Stop Operation
266
PWM6 and PWM6, Single Mode / Repeat Mode (P67MD="0", Pnmd="0")
268
PWM6 and PWM7, Single Mode / One Shot Mode (P67MD="0", Pnmd="1")
270
PWM6 and PWM7, Coupled Mode (with no Dead-Time Specified) / Repeat Mode (P67MD="1", P6DTMD="0", P6MD="0")
272
PWM6 and PWM7, Coupled Mode (with no Dead-Time Specified) / One Shot Mode (P67MD="1", P6DTMD="0", P6MD="1")
274
PWM6 and PWM7, Coupled Mode (with Dead-Time Specified) / Repeat Mode (P67MD="1", P6DTMD="1", P6MD="0")
276
PWM6 and PWM7, Coupled Mode (with Dead-Time Specified) / One Shot Mode (P67MD="1", P6DTMD="1", P6MD="1")
279
PWM6/PWM7 Start/Stop/Clear Operation by the External Control
282
Software Start Mode
283
External Input Start Mode
285
Software Start or External Input Clear Mode
287
Emergency Stop Operation
290
Chapter 12 Synchronous Serial Port

292
- Synchronous Serial Port (SSIO)
  293
- General Description
  293
- Features
  293
- Configuration
  293
- List of Pins
  294
- Description of Registers
  295
- List of Registers
  295
- Serial Port 0 Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
  296
- Serial Port 0 Control Register (SIO0CON)
  297
- Serial Port 0 Mode Register 0 (SIO0MOD0)
  298
- Serial Port 0 Mode Register 1 (SIO0MOD1)
  299
- Description of Operation
  300
- Transmit Operation
  300
- Receive Operation
  301
- Transmit/Receive Operation
  302
- Specifying Port Registers
  303
- Functioning P42 (SOUT0: Output), P41 (SCK0: Input/Output), and P40 (SIN0: Input) as the SSIO0/ "Master Mode
  303
- Functioning P42 (SOUT0: Output), P41 (SCK0: Input/Output), and P40 (SIN0: Input) as the SSIO0/ "Slave Mode
  304
- Uart
  305
- Features
  306
- Configuration
  306
- UART0 Transmit/Receive Buffer (UA0BUF)
  308
- UART1 Transmit/Receive Buffer (UA1BUF)
  309
- UART0 Control Register (UA0CON)
  310
- UART1 Control Register (UA1CON)
  310
- UART0 Mode Register 0 (UA0MOD0)
  311
- UART1 Mode Register 0 (UA1MOD0)
  313
- UART0 Mode Register 1 (UA0MOD1)
  315
- UART1 Mode Register 1 (UA1MOD1)
  317
- UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
  319
- UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)
  320
- UART0 Status Register (UA0STAT)
  321
- UART1 Status Register (UA1STAT)
  323
- Description of Operation
  325
- Transfer Data Format
  325
- Baud Rate
  326
- Transmit Data Direction
  327
- Transmit Operation
  328
- Receive Operation
  330
- Detection of Start Bit
  332
- Sampling Timing
  332
- Receive Margin
  333
- Specifying Port Registers
  334
- Functioning P53 (TXD1: Output) and P54 Pins (RXD0: Input) as the UART (Full-Duplex)
  334
- Functioning P43 (TXD1: Output) and P02 Pins (RXD0: Input) as the UART (Full-Duplex)
  335
- Functioning P85 (TXD1: Output) and P86 Pins (RXD0: Input) as the UART (Full-Duplex)
  337
- Functioning P53 (TXD1: Output) and P03 Pins (RXD1: Input) as the UART (Half-Duplex)
  338
- Functioning P55 (TXD0: Output) and P42 Pins (RXD0: Input) as the UART (Half-Duplex)
  340
- Functioning P43 (TXD0: Output) and P54 Pins (RXD0: Input) as the UART (Half-Duplex)
  342
- Functioning P85 (TXD1: Output) and P72 Pins (RXD1: Input) as the UART (Half-Duplex)
  344
- I C Bus Interface
  346
- Features
  347
- Configuration
  347
- List of Pins
  348
- Description of Registers
  349
- List of Registers
  349
- C Bus 0 Receive Register (I2C0RD)
  349
- I 2 C Bus 0 Slave Address Register (I2C0SA)
  351
- I 2 C Bus 0 Transmit Data Register (I2C0TD)
  352
- I 2 C Bus 0 Control Register (I2C0CON)
  353
- I 2 C Bus 0 Mode Register (I2C0MOD)
  354
- I 2 C Bus 0 Status Register (I2C0STAT)
  356
- Description of Operation
  357
- Communication Operating Mode
  357
- Start Condition
  357
- Restart Condition
  357
- Slave Address Transmit Mode
  357
- Data Transmit Mode
  357
- Data Receive Mode
  357
- Control Register Setting Wait State
  357
- Stop Condition
  357
- Communication Operation Timing
  358
- Operation Waveforms
  360
- Specifying Port Registers
  361
- Functioning P41(SCL) and P40(SDA) as the I2C
  361
- Port 0
  363
- Features
  363
- Configuration
  363
- List of Pins
  364
- Description of Registers
  365
- List of Registers
  365
- Port 0 Data Register (P0D)
  366
- Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
  367
- External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)
  368
- External Interrupt Control Register 2 (EXICON2)
  369
- Description of Operation
  371
- External Interrupt
  371
- Interrupt Request
  371
- Port 1
  374
- General Description
  374
- Features
  374
- Configuration
  374
- List of Pins
  374
- Description of Registers
  375
- List of Registers
  375
- Port 1 Data Register (P1D)
  376
- Port 1 Direction Register (P1DIR)
  377
- Port 1 Control Registers 0,1 (P1CON0, P1CON1)
  378
- Description of Operation
  380
- Input Port Function
  380
- Features
  382
- Configuration
  382
- List of Pins
  382
- Description of Registers
  383
- List of Registers
  383
- Port 2 Data Register (P2D)
  384
- Port 2 Control Registers 0, 1 (P2CON0, P2CON1)
  385
- Port 2 Mode Register (P2MOD)
  387
- Description of Operation
  389
- Output Port Function
  389
- Secondary, Tertiary, and Quartic Functions
  389
- Port 3
  391
- General Description
  391
- Features
  391
- Configuration
  392
- List of Pins
  393
- Description of Registers
  394
- List of Registers
  394
- Port 3 Data Register (P3D)
  395
- Port 3 Direction Register (P3DIR)
  397
- Port 3 Control Registers 0, 1 (P3CON0, P3CON1)
  398
- Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
  400
- Description of Operation
  402
- Input/Output Port Functions
  402
- Secondary and Tertiary Functions
  402
- External Interrupt
  402
- Interrupt Request
  402
- Port 4
  404
- Features
  404
- Configuration
  404
- List of Pins
  405
- Port 4 Data Register (P4D)
  407
- Port 4 Direction Register (P4DIR)
  409
- Port 4 Control Registers 0, 1 (P4CON0, P4CON1)
  410
- Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
  412
- Description of Operation
  415
- Input/Output Port Functions
  415
- Secondary, Tertiary, and Quartic Functions
  415
- Port 5
  417
- General Description
  417
- Features
  417
- Configuration
  417
- List of Pins
  418
- Port 5 Data Register (P5D)
  420
- Port 5 Direction Register (P5DIR)
  421
- Port 5 Control Registers 0, 1 (P5CON0, P5CON1)
  422
- Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1)
  424
- Description of Operation
  427
- Input/Output Port Functions
  427
- Secondary, Tertiary, and Quartic Functions
  427
- Port 6
  429
- Features
  429
- Configuration
  429
- List of Pins
  430
- Port 6 Data Register (P6D)
  432
- Port 6 Direction Register (P6DIR)
  433
- Port 6 Control Registers 0, 1 (P6CON0, P6CON1)
  434
- Port 6 Mode Registers 0, 1 (P6MOD0, P6MOD1)
  436
- Description of Operation
  438
- Input/Output Port Functions
  438
- Secondary, Tertiary, and Quartic Functions
  438
- Port 7
  440
- Features
  440
- Configuration
  440
- List of Pins
  441
- Description of Registers
  442
- List of Registers
  442
- Port 7 Data Register (P7D)
  443
- Port 7 Direction Register (P7DIR)
  444
- Port 7 Control Registers 0, 1 (PCCON0, PCCON1)
  445
- Port 7 Mode Registers 0, 1 (P7MOD0, P7MOD1)
  447
- Description of Operation
  449
- Input/Output Port Functions
  449
- Secondary and Tertiary Functions
  449
- Port 8
  451
- Features
  451
- Configuration
  451
- List of Pins
  452
- Description of Registers
  453
- List of Registers
  453
- Port 8 Data Register (P8D)
  454
- Port 8 Direction Register (P8DIR)
  455
- Port 8 Control Registers 0, 1 (P8CON0, P8CON1)
  456
- Port 8 Mode Registers 0, 1 (P8MOD0, P8MOD1)
  458
- Description of Operation
  460
- Input/Output Port Functions
  460
- Secondary and Tertiary Functions
  460
- Successive Approximation Type A/D Converter (SA-ADC)
  462
- Features
  462
- Configuration
  462
- SA-ADC Result Register 0L (SADR0L)
  465
- SA-ADC Result Register 0H (SADR0H)
  465
- SA-ADC Result Register 1L (SADR1L)
  466
- SA-ADC Result Register 1H (SADR1H)
  466
- SA-ADC Result Register 2L (SADR2L)
  467
- SA-ADC Result Register 2H (SADR2H)
  467
- SA-ADC Result Register 3L (SADR3L)
  468
- SA-ADC Result Register 3H (SADR3H)
  468
- SA-ADC Result Register 4L (SADR4L)
  469
- SA-ADC Result Register 4H (SADR4H)
  469
- SA-ADC Result Register 5L (SADR5L)
  470
- SA-ADC Result Register 5H (SADR5H)
  470
- SA-ADC Result Register 6L (SADR6L)
  471
- SA-ADC Result Register 6H (SADR6H)
  471
- SA-ADC Result Register 7L (SADR7L)
  472
- SA-ADC Result Register 7H (SADR7H)
  472
- SA-ADC Result Register 8L (SADR8L)
  473
- SA-ADC Result Register 8H (SADR8H)
  473
- SA-ADC Result Register 9L (SADR9L)
  474
- SA-ADC Result Register 9H (SADR9H)
  474
- SA-ADC Result Register al (SADRAL)
  475
- SA-ADC Result Register AH (SADRAH)
  475
- SA-ADC Result Register BL (SADRBL)
  476
- SA-ADC Result Register BH (SADRBH)
  476
- SA-ADC Control Register 0 (SADCON0)
  477
- SA-ADC Control Register 1 (SADCON1)
  478
- SA-ADC Mode Register 0 (SADMOD0)
  479
- SA-ADC Mode Register 1 (SADMOD1)
  481
- Description of Operation
  482
- Analogue Comparator
  485
- General Description
  485
- Features
  485
- Configuration
  485
- List of Pins
  485
- Description of Registers
  486
- List of Registers
  486
- Comparator 0 Control Register 0 (CMP0CON0)
  487
- Comparator 0 Control Register 1 (CMP0CON1)
  488
- Description of Operation
  489
- Comparator Functions
  489
- Interrupt Request
  490
- LLD (Low Level Detector)
  491
Chapter 26 LLD Circuit

492
- General Description
  492
- Features
  492
- Configuration
  492
- Description of Registers
  493
- List of Registers
  493
- LLD Circuit Control Register 1 (LLDCON1)
  494
- Threshold Voltage
  495
- Operation of LLD Circuit
  496
- Power Supply Circuit
  497
- Features
  498
- Configuration
  498
- List of Pins
  498
- Description of Operation
  499
- On-Chip Debug Function
  500
- How to Connect the On-Chip Debug Emulator
  501
- FLASH Memory Rewrite Function
  503
- Features
  503
- Description of Registers
  504
- List of Registers
  504
- Flash Control Register (FLASHCON)
  510
- Flash Acceptor (FLASHACP)
  511
- Flash Segment Register (FLASHSEG)
  511
- Flash Self Register (FLASHSLF)
  512
- Flash Remap Register (REMAPADD)
  513
- Description of Operation
  514
- Block Erase Function
  516
- Sector Erase Function
  517
- 1-Word Write Function
  518
- Boot Area Remap Function by Software
  519
- Notes in Use
  520
- Code-Option
  521
- Code-Option Register 0 (CODEOP0)
  523
- The Setting Method of the Code-Option Data
  524
- Code-Option Data Format
  524
- Code-Option Programming Method
  524
Appendix A Contents of Registers

526
Appendix A Registers

526
Appendix B Package Dimensions

534
Appendix B Package Dimentions

534
Appendix C Electrical Characteristics

539
Appendix D Application Circuit Example

550
Appendix E Check List

552
- Revision History
  555

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Rohm LAPIS ML620Q152A Manuals

Rohm LAPIS ML620Q152A User Manual (556 pages)

Table of Contents

Chapter 12 Synchronous Serial Port

Chapter 26 LLD Circuit

Appendix A Contents of Registers

Appendix A Registers

Appendix B Package Dimensions

Appendix B Package Dimentions

Appendix C Electrical Characteristics

Appendix D Application Circuit Example

Appendix E Check List

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