Toshiba TXZ+ TMPM4GRF20FG Manuals

Manuals and User Guides for Toshiba TXZ+ TMPM4GRF20FG. We have 1 Toshiba TXZ+ TMPM4GRF20FG manual available for free PDF download: Reference Manual

Toshiba TXZ+ TMPM4GRF20FG Reference Manual (93 pages)

32-bit RISC microcontroller

Brand: Toshiba | Category: Microcontrollers | Size: 1 MB

TMPM4G Group
1
Table of Contents
2
Preface
7
Related Document
7
Conventions
8
Terms and Abbreviations
10
Clock Control and Operation Mode
11
Outlines
11
Clock Control
11
Clock Type
11
Initial Value by Reset Operation
12
Clock System Diagram
13
Figure 1.1 Clock System Diagram
13
Warming-Up Function
14
Warming-Up Timer for High-Speed Oscillation
14
Warming-Up Timer for Low-Speed Oscillation
15
Directions for Warming-Up Timer
15
Clock Multiplying Circuit (PLL) for Fsys
16
PLL Setup after Reset Release
16
Formula and Example of Setting of PLL Multiplication Value
16
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup
16
Table 1.2 PLL Correction Value (Example)
17
Table 1.3 PLL0SET Setting Value (Example)
17
Change of PLL Multiplication Value under Operation
18
PLL Operation Start/Stop/Switching Procedure
19
System Clock
20
Table 1.4 Clock Domains of CPU and Peripherals
20
Table 1.5 Time Interval for Changing System Clock
20
Table 1.6 Example of Operating Frequency
21
Table 1.7 Operating Frequency Examples of High-Speed and Middle-Speed System Clocks
21
Setting Method of System Clock
22
Low-Speed Clock
24
Clock Supply Setting Function
25
Prescaler Clock
25
Table 1.8 Time Interval for Changing Prescaler Clock
25
Operation Mode
26
Details of Operation Mode
26
Feature in each Mode
26
Transition to and Return from Low-Power Consumption Mode
27
Selection of Low-Power Consumption Mode
27
Table 1.9 Low-Power Consumption Mode Selection
27
Peripheral Function State in Low-Power Consumption Mode
28
Table 1.10 Block Operation Status in each Low-Power Consumption Mode
28
Mode State Transition
30
IDLE Mode Transition Flow
30
Figure 1.2 Change State Transition
30
STOP1 Mode Transition Flow
31
STOP2 Mode Transition Flow
32
Return Operation from Low-Power Consumption Mode
33
Release Source of Low-Power Consumption Mode
33
Table 1.11 Release Source List
33
Warming up at Release of Low-Power Consumption Mode
35
Table 1.12 Warming up
35
Restart Operation from STOP2 Mode
36
Figure 1.3 STOP2 Mode Restart Operation Flow
36
Clock Operation by Mode Transition
37
NORMAL → IDLE → NORMAL Operation Mode Transition
37
NORMAL → STOP1 → NORMAL Operation Mode Transition
37
Figure 1.4 NORMAL → STOP1 → NORMAL Operation Mode Transition
37
NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
38
Figure 1.5 NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
38
Registers
39
List of Registers
39
Clock Control and Operation Mode
39
Low-Speed Oscillation/Power Control (Note1, Note2)
39
Details of Register
40
CGPROTECT] (CG Write Protection Register)
40
CGOSCCR] (Oscillation Control Register)
40
CGSYSCR] (System Clock Control Register)
41
CGSTBYCR] (Standby Control Register)
42
CGPLL0SEL] (PLL Selection Register for Fsys)
42
CGWUPHCR] (High-Speed Oscillation Warming-Up Register)
43
CGWUPLCR] (Low-Speed Oscillation Warming-Up Register)
43
CGFSYSMENC] (Middle-Speed Clock Supply and Stop Register C for Fsysm)
44
CGFSYSMENA] (Middle-Speed Clock Supply and Stop Register a for Fsysm)
45
CGFSYSMENB] (Middle-Speed Clock Supply and Stop Register B for Fsysm)
47
CGFSYSENA] (High-Speed Clock Supply and Stop Register a for Fsysh)
49
CGFCEN] (Clock Supply and Stop Register for Fc)
50
CGSPCLKEN] (Clock Supply for ADC and Debug Circuit Register)
50
CGEXTEND2] (Function Extension Register 2)
51
RLMLOSCCR] (Low-Speed Oscillation and Internal High-Speed Oscillation 2 Clock Control Register)
51
RLMSHTDNOP] (Power Supply Cut off Control Register)
52
RLMPROTECT] (RLM Write Protection Register)
52
Information for each Product
53
Cgfsysena]
53
Table 1.13 Allocation of [CGFSYSENA] by each Product
53
Cgfsysmena]
54
Table 1.14 Allocation of [CGFSYSMENA] by each Product
54
Cgfsysenb]
55
Table 1.15 Allocation of [CGFSYSMENB] by each Product
55
Cgfsysenc]
56
Table 1.16 Allocation of [CGFSYSMENC] by each Product
56
Cgfcen]
57
Table 1.17 Allocation of [CGFCEN] by each Product
57
Memory Map
58
Outline
58
Tmpm4Gxf20
59
Figure 2.1 Tmpm4Gxf20
59
Tmpm4Gxf15
60
Figure 2.2 Tmpm4Gxf15
60
Tmpm4Gxf10
61
Figure 2.3 Tmpm4Gxf10
61
Tmpm4Gxfd
62
Figure 2.4 Tmpm4Gxfd
62
Bus Matrix
63
Configuration
64
Single Chip Mode
64
Figure 2.5 Single Chip Mode
64
Single Boot Mode
65
Figure 2.6 Single Boot Mode
65
Connection Table
66
Code Area/Sram Area/Smif Area/External Bus Area
66
Table 2.1 Tmpm4Gxf20 Single Chip Mode
66
Table 2.2 Tmpm4Gxf20 Single Boot Mode
67
Table 2.3 Tmpm4Gxf15 Single Chip Mode
68
Table 2.4 Tmpm4Gxf15 Single Boot Mode
69
Table 2.5 Tmpm4Gxf10 Single Chip Mode
70
Table 2.6 Tmpm4Gxf10 Single Boot Mode
71
Table 2.7 Tmpm4Gxfd Single Chip Mode
72
Table 2.8 Tmpm4Gxfd Single Boot Mode
73
Peripheral Area
74
Table 2.9 Peripheral Area
74
RAM Access
75
List of Registers
75
Table 2.10 Number of Clocks to Access each RAM
75
Details of Register
76
Reset and Power Control
77
Outlines
77
Function and Operation
78
Cold Reset
78
Reset by Power-On Reset Circuit (Without Using RESET_N Pin)
79
Figure 3.1 Reset Operation by Power-On Reset Circuit
79
Reset by RESET_N Pin
80
Figure 3.2 Reset Operation by RESET_N Pin (1)
80
Figure 3.3 Reset Operation by RESET_N Pin (2)
81
Continuation of Reset by LVD
82
Figure 3.4 Reset Operation by LVD Reset
82
Warm Reset
83
Warm Reset by REST_N Pin
83
Warm Reset by Internal Reset
83
Figure 3.5 Warm Reset Operation
83
Reset by STOP2 Mode Release
84
Starting Single Boot Mode
85
Starting Single Boot Mode by RESET_N Pin
85
Figure 3.6 Starting Single Boot Mode by RESET_N Pin
85
Starting Single Boot Mode by Power-On Reset (Not Using RESET_N Pin)
86
Figure 3.7 Starting Single Boot Mode by Power-On Reset (Not Using RESET_N Pin)
86
Starting Single Boot Mode When Power Supply Is Stable
87
Figure 3.8 Starting Single Boot Mode When Power Supply Is Stable
87
Power-On Reset Circuit
88
Operation at Time of Turn on
88
Operation at Time of Turn off
88
Figure 3.9 Power-On Reset Circuit
88
Precautions When Turning off Power
89
Figure 3.10 Falling Gradient When Turning off Power
89
About Turn on Power Supply after Turn off
90
When Using External Reset Circuit or Internal LVD Reset Output
90
When Not Using External Reset Circuit and Internal LVD Reset Output
90
When Boundary Scan Is Used
90
After Reset Release
90
Reset Factor and Reset Range
91
Table 3.1 Reset Factor and Range Initialized
91
Revision History
92
Table 4.1 Revision History
92
Restrictions on Product Use
93

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Toshiba TXZ+ TMPM4GRF20FG Reference Manual (93 pages)

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