31St Local Oscillator Circuits - Icom IC-730 Maintenance Manual

3 – 3 1ST LOCAL OSCILLATOR CIRCUITS
The 1st local oscillator employs a premix system consisting of
a PLL and a crystal oscillator for each band.
1. PLL (PHASE LOCKED LOOP) CIRCUITS
The PLL employs a mixed down type, and is locked in 10kHz
steps. This output is divided into 1/10, as a result, 1kHz steps
is obtained.
The local oscillator, Q1 oscillates at 13. 666MHz with the
crystal unit X2. This signal is tripled at Q2 and Q3, thus the
local oscillator output, 123MHz is obtained. A varactor diode,
Q1 is connected in series with X2, and voltages from the RIT
control and FREQUENCY SET control are applied to the
cathode and anode respectively. This varies the local
oscillator frequency slightly to provide the RIT function and
frequency calibration.
Q6 is the VCO (Voltage Controlled Oscillator), and oscillates
at a frequency between 132MHz and 139MHz. The
The divided signal is fed to the phase detector internally. The
phase detector detects the phase difference between the
10KHz reference signal and the output signal from the
programmable divider, and proportionately puts out
positive/negative pulse signal at pin 14.
This pulse signal is fed to the loop filter consisting of R28
through R30 and C34 through C36, then fed to the varactor
diode, D2, to lock the VCO frequency.
The locked VCO signal is fed to the buffer amplifier, Q7, and
a part of this signal is fed to the 1/10 divider, IC2. Then the
divided signal, between 13.2MHz and 13.9MHz with 1KHz
steps, is fed to the mixer in the PREMIX unit through low-
pass filter consisting of C53 through C57, L10 and L 11, and
attenuator consisting of R41 through R43.
2. PREMIX CIRCUITS
The premix circuits are composed of offset frequency
oscillator for each band, mixer and band-pass filter for each
band.
Q1 through Q11 are offset frequency oscillators. One of them
is selected by the band signal from the band switch
output signal is fed to the base of Q4, PLL mixer, through
buffer amplifiers Q7 and Q8. To the emitter of Q4, the local
oscillator signal is fed and mixed with the VCO signal to mix
down the VCO frequency.
The output signal from the mixer is fed to the low-pass filter
consisting of C23, LS and C24, to filter out only the signal
below 15MHz. Then the signal is amplified to the proper level
(more than 3V P-P) of the programmable divider, IC1, by Q5.
IC1, PLL IC, consists of the programmable divider, reference
frequency oscillator, fixed divider, phase detector, etc. The
reference frequency oscillator oscillates at 9.000 MHz, and its
signal is divided into 1OkHz and fed to the phase detector as
the reference frequency.
The signal from Q5 is divided into 1/ N at the programmable
divider. The N data is sent from the CPU in the LOGIC unit in
sequence as shown in the illustration.
and oscillates at the frequency shown in the table for each
band.
Band
3.5
7.0
10.0
14.0
18.0
21.0
24.0
28.0
28.5
29.0
29.5
The offset frequency signal is fed to the doubly balanced
mixer consisting of D1 through D4, and L12 and L13. To the
other port of the mixer, the PLL output signal is applied to
convert into the 1st local oscillator signal.
3 – 6
Offset Frequency
29.9315 MHz
33.4315 MHz
36.4315 MHz
40.4315 MHz
44.4315 MHz
47.4315 MHz
50.9315 MHz
54.4315 MHz
54.9315 MHz
55.4315 MHz
55.9315MHz